PIC18F2410-I/ML Microchip Technology, PIC18F2410-I/ML Datasheet - Page 139

• Manufacturer Part Number: PIC18F2410-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2410-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured
CCP1M3:CCP1M0 bits of the CCP1CON register.
Figure 15-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Delay register, PWM1CON, which is loaded
at either the duty cycle boundary or the period bound-
ary (whichever comes first). Because of the buffering,
the module waits until the assigned timer resets instead
of starting immediately. This means that Enhanced
PWM waveforms do not exactly match the standard
PWM waveforms, but are instead offset by one full
instruction cycle (4 T
As before, the user must manually configure the
appropriate TRIS bits for output.
FIGURE 15-1:
© 2009 Microchip Technology Inc.
Enhanced PWM Mode
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time
CCPR1H (Slave)
Duty Cycle Registers
Comparator
by
base.
CCPR1L
PR2
TMR2
Comparator
setting
OSC
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
).
(Note 1)
the
Clear Timer,
set CCP1 pin and
latch D.C.
CCP1CON<5:4>
P1M1:P1M0
R
S
P1M1<1:0>
Q
and
PWM1CON
Controller
15.4.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
• The PWM duty cycle is copied from CCPR1L into
Output
2
CCP1/P1A
CCP1 pin will not be set)
CCPR1H
Note:
P1B
P1C
P1D
PIC18F2X1X/4X1X
PWM Period = [(PR2) + 1] • 4 • T
CCP1M<3:0>
4
PWM PERIOD
The Timer2 postscaler (see Section 12.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
TRISx<x>
TRISx<x>
TRISx<x>
TRISx<x>
(TMR2 Prescale Value)
DS39636D-page 141
CCP1/P1A
P1B
P1C
P1D
OSC
•