PIC18F2410-I/ML Microchip Technology, PIC18F2410-I/ML Datasheet - Page 241

IC PIC MCU FLASH 8KX16 28QFN

PIC18F2410-I/ML

Manufacturer Part Number
PIC18F2410-I/ML
Description
IC PIC MCU FLASH 8KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2410-I/ML

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2410-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
REGISTER 22-4:
REGISTER 22-5:
© 2009 Microchip Technology Inc.
bit 7
bit 6-3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5-3
bit 2
bit 1
bit 0
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
Legend:
R = Readable bit
-n = Value when device is unprogrammed
MCLRE: MCLR Pin Enable bit
1 = MCLR pin enabled; RE3 input pin disabled
0 = RE3 input pin enabled; MCLR disabled
Unimplemented: Read as ‘0’
LPT1OSC: Low-Power Timer1 Oscillator Enable bit
1 = Timer1 configured for low-power operation
0 = Timer1 configured for higher power operation
PBADEN: PORTB A/D Enable bit
(Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration.)
1 = PORTB<4:0> pins are configured as analog input channels on Reset
0 = PORTB<4:0> pins are configured as digital I/O on Reset
CCP2MX: CCP2 Mux bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Legend:
R = Readable bit
-n = Value when device is unprogrammed
DEBUG: Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug
XINST: Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
Unimplemented: Read as ‘0’
LVP: Single-Supply ICSP Enable bit
1 = Single-Supply ICSP enabled
0 = Single-Supply ICSP disabled
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack full/underflow will cause Reset
0 = Stack full/underflow will not cause Reset
bit 7
bit 7
MCLRE
DEBUG
R/P-1
R/P-1
XINST
R/P-0
U-0
C = Clearable bit
P = Programmable bit
U-0
U-0
U-0
U-0
PIC18F2X1X/4X1X
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U-0
U-0
LPT1OSC
R/P-0
R/P-1
LVP
PBADEN
R/P-1
U-0
DS39636D-page 243
CCP2MX
STVREN
R/P-1
R/P-1
bit 0
bit 0

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