PIC18F2410-I/ML Microchip Technology, PIC18F2410-I/ML Datasheet - Page 261

IC PIC MCU FLASH 8KX16 28QFN

PIC18F2410-I/ML

Manufacturer Part Number
PIC18F2410-I/ML
Description
IC PIC MCU FLASH 8KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2410-I/ML

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2410-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 23-2:
© 2009 Microchip Technology Inc.
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
Note 1:
Mnemonic,
Operands
2:
3:
4:
When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared
if assigned.
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
n
n
n
n
n
n
n
n
n
n, s
n
n
s
k
s
PIC18FXXXX INSTRUCTION SET (CONTINUED)
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into Standby mode
Description
2nd word
2nd word
1
1
1 (2 or 3)
1 (2 or 3)
1
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
1
1
2
1
1
1
1
2
1
2
2
2
1
Cycles
1001
1000
1011
1010
0111
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
MSb
16-Bit Instruction Word
PIC18F2X1X/4X1X
bbba
bbba
bbba
bbba
bbba
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
ffff
ffff
ffff
ffff
ffff
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
ffff
ffff
ffff
ffff
ffff
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
LSb
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
TO
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO
DS39636D-page 263
,
,
Affected
PD
PD
Status
1, 2
1, 2
3, 4
3, 4
1, 2
4
Notes

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