PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 59
PIC18F27J53-I/SP
Manufacturer Part Number
PIC18F27J53-I/SP
Description
IC PIC MCU 128KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/SP
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
DIP
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F27J53-I/SP
Manufacturer:
MITSUBISHI
Quantity:
12
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 59 of 586
- Download datasheet (6Mb)
REGISTER 4-3:
REGISTER 4-4:
REGISTER 4-5:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
U-0
—
Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and V
DSBOR threshold, or DSBOR is enabled or disabled, but V
Sleep or the device is in Deep Sleep and the dedicated DSBOR is enabled and V
DSBOR threshold, or DSBOR is enabled or disabled, but V
All register bits are maintained unless: V
All register bits are maintained unless: V
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Deep Sleep Persistent General Purpose bits
Contents are retained even in Deep Sleep mode.
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
U-0
—
DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0
(BANKED F4Eh)
DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1
(BANKED F4Fh)
DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
U-0
Deep Sleep Persistent General Purpose bits
—
Deep Sleep Persistent General Purpose bits
U-0
Preliminary
—
DDCORE
DDCORE
R/W-xxxx
R/W-xxxx
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
drops below the normal BOR threshold outside of Deep
drops below the normal BOR threshold outside of Deep
PIC18F47J53 FAMILY
(1)
(1)
U-0
—
DD
DD
is hard cycled to near V
is hard cycled to near V
U-0
—
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
DD
DD
U-0
—
drops below the
drops below the
SS
SS
.
.
DS39964B-page 59
DSINT0
R/W-0
bit 0
bit 0
bit 0
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