DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 12

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
FIGURE 1-1:
DS70178C-page 10
OSC1/CLK1
Control Signals
to Various Blocks
Program Memory
Controller
Address Latch
Interrupt
Data Latch
(12 Kbytes)
Comparator
Module
SPI1
24
Generation
Timing
Instruction
Decode &
Control
16
MCLR
24
24
Control Block
PSV & Table
Data Access
24
10-bit ADC
Timers
dsPIC30F1010 BLOCK DIAGRAM
16
Control
Start-up Timer
Stack
Logic
PCU
Program Counter
Watchdog
Power-up
Oscillator
Y Data Bus
Reset
Timer
Timer
POR
8
ROM Latch
Notification
PCH
Change
IR
Input
Control
Logic
Loop
16
PCL
Decode
16
Engine
16
DSP
Compare
Output
Module
SMPS
PWM
Data Latch
(256 bytes)
Y AGU
Address
Y Data
Effective Address
Preliminary
Latch
RAM
16
16
16
W Reg Array
16
ALU<16>
16 x 16
16
16
16
X RAGU
X WAGU
X Data Bus
16
Data Latch
Divide
(256 bytes)
UART1
Address
Unit
X Data
I
Latch
2
RAM
C™
16
16
16
16
PORTA
PORTD
PORTE
PORTF
PORTB
© 2006 Microchip Technology Inc.
U1ARX/CN0/RE6
SFLT2/INT0/OCFLTA/RA9
PGC2/EMUC2/OC1/SFLT1/
INT1/RD0
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
RE4
RE5
PGC1/EMUC1/EXTREF/T1CK/
PGD1/EMUD1/T2CK/U1ATX/
CN1/RE7
PGD2/EMUD2/SCK1/SFLT3/
INT2/RF6
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SD01/SCL/U1TX/RF8
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CN6/RB4
AN5/CMP2D/CN7/RB5
OSC1/CLKI/RB6
OSC2/CLKO/RB7