DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 80

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
6.2
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (V
converted.
When reading the PORT register, all pins configured as
analog input channel will read as cleared (a low level).
Pins configured as digital inputs will not convert an ana-
log input. Analog levels on any pin that is defined as a
digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
6.2.1
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 6-1:
DS70178C-page 78
MOV 0xFF00, W0; Configure PORTB<15:8>
MOV W0, TRISBB; and PORTB<7:0> as outputs
NOP
BTSS PORTB, #13; Next Instruction
; as inputs
; Delay 1 cycle
Configuring Analog Port Pins
I/O PORT WRITE/READ TIMING
PORT WRITE/READ
EXAMPLE
OH
or V
OL
) will be
Preliminary
6.3
The input change notification function of the I/O ports
allows the dsPIC30F1010/202X devices to generate
interrupt requests to the processor in response to a
change-of-state on selected input pins. This feature is
capable of detecting input change-of-states even in
Sleep mode, when the clocks are disabled. There are
8 external signals (CN0 through CN7) that can be
selected (enabled) for generating an interrupt request
on a change-of-state.
There are two control registers associated with the CN
module. The CNEN1 register contain the CN interrupt
enable (CNxIE) control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
register, which contain the weak pull-up enable (CNx-
PUE) bits for each of the CN pins. Setting any of the
control bits enables the weak pull-ups for the
corresponding pins.
Note: Pull-ups on change notification pins should
always be disabled whenever the port pin is
configured as a digital output.
Input Change Notification
© 2006 Microchip Technology Inc.