DSPIC33FJ16GS502-I/SO Microchip Technology, DSPIC33FJ16GS502-I/SO Datasheet - Page 102

• Manufacturer Part Number: DSPIC33FJ16GS502-I/SO
• Description: IC DSPIC MCU/DSP 16K 28-SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 16KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 7-1:
REGISTER 7-2:
DS70318D-page 100
bit 15
bit 7
Legend:
C = Clearable bit
S = Settable bit
‘1’ = Bit is set
bit 7-5
bit 15
bit 7
Legend:
R = Readable bit
0’ = Bit is cleared
bit 3
Note 1: For complete register details, see Register 3-1.
Note 1: For complete register details, see Register 3-2.
R/W-0
IPL2
R/W-0
SATA
R-0
U-0
OA
—
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
3: The IPL<2:0> status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
(2)
(3)
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
IPL3: CPU Interrupt Priority Level Status bit 3
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
R/W-0
IPL1
R/W-0
SATB
R-0
U-0
OB
—
CORCON: CORE CONTROL REGISTER
SR: CPU STATUS REGISTER
(2)
(3)
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
C = Clearable bit
W = Writable bit
‘x = Bit is unknown
R/W-0
SATDW
IPL0
R/W-1
R/C-0
U-0
SA
—
(2)
(3)
ACCSAT
R/W-0
R/C-0
R-0
U-0
RA
US
SB
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
-n = Value at POR
U = Unimplemented bit, read as ‘0’
(2)
IPL3
R/W-0
R/W-0
R/C-0
OAB
EDT
R-0
N
(2)
(2)
(1)
R/W-0
R/W-0
R/C-0
SAB
PSV
R-0
OV
© 2009 Microchip Technology Inc.
‘1’ = Bit is set
DL<2:0>
R/W-0
R/W-0
RND
R -0
R-0
DA
Z
R/W-0
R/W-0
R/W-0
R-0
DC
IF
C
bit 8
bit 0
bit 8
bit 0