DSPIC33FJ16GS502-I/SO Microchip Technology, DSPIC33FJ16GS502-I/SO Datasheet - Page 256

IC DSPIC MCU/DSP 16K 28-SOIC

DSPIC33FJ16GS502-I/SO

Manufacturer Part Number
DSPIC33FJ16GS502-I/SO
Description
IC DSPIC MCU/DSP 16K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-I/SO

Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
16KB
Supply Voltage Range
3V To 3.6V
Package
28SOIC W
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ16GS502-I/SO
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DSPIC33FJ16GS502-I/SO
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 19-7:
DS70318D-page 254
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
Note 1: This register is only implemented on the dsPIC33FJ16GS504 devices.
IRQEN5
IRQEN4
R/W-0
R/W-0
2: If other conversions are in progress, then conversion will be performed when the conversion resources are
available.
IRQEN5: Interrupt Request Enable 5 bit
1 = Enable IRQ generation when requested conversion of channels AN11 and AN10 is completed
0 = IRQ is not generated
PEND5: Pending Conversion Status 5 bit
1 = Conversion of channels AN11 and AN10 is pending; set when selected trigger is asserted
0 = Conversion is complete
SWTRG5: Software Trigger 5 bit
1 = Start conversion of AN11 and AN10 (if selected in TRGSRC bits)
This bit is automatically cleared by hardware when the PEND5 bit is set.
0 = Conversion is not started
PEND5
PEND4
R/W-0
R/W-0
ADCPC2: A/D CONVERT PAIR CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
SWTRG5
SWTRG4
R/W-0
R/W-0
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
TRGSRC5<4:0>
TRGSRC4<4:0>
R/W-0
R/W-0
(2)
© 2009 Microchip Technology Inc.
(1)
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0

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