DSPIC33FJ16GS502-I/SO Microchip Technology, DSPIC33FJ16GS502-I/SO Datasheet - Page 92

• Manufacturer Part Number: DSPIC33FJ16GS502-I/SO
• Description: IC DSPIC MCU/DSP 16K 28-SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS502-I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 16KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
6.1
The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/
X04 families of devices have two types of Reset:
• Cold Reset
• Warm Reset
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC Configuration bits in the FOSC Configuration
register select the device clock source.
A warm Reset is the result of all the other Reset
sources, including the RESET instruction. On warm
Reset, the device will continue to operate from the
current clock source as indicated by the Current
Oscillator Selection (COSC<2:0>) bits in the Oscillator
Control (OSCCON<14:12>) register.
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure 6-2.
1.
TABLE 6-1:
DS70318D-page 90
FRC, FRCDIV16, FRCDIVN
FRCPLL
XT
HS
EC
XTPLL
HSPLL
ECPLL
LPRC
Note 1:
POR Reset: A POR circuit holds the device in
Reset when the power supply is turned on. The
POR circuit is active until V
threshold and the delay, T
Oscillator Mode
2:
3:
System Reset
T
times vary with crystal characteristics, load capacitance, etc.
T
10 MHz crystal and T
T
OSCD
OST
LOCK
= Oscillator start-up timer delay (1024 oscillator clock period). For example, T
OSCILLATOR DELAY
= PLL lock time (1.5 ms nominal) if PLL is enabled.
= Oscillator start-up delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal oscillator start-up
POR
DD
OST
Startup Delay
, has elapsed.
crosses the V
Oscillator
T
T
T
T
T
T
T
= 32 ms for a 32 kHz crystal.
OSCD (1)
OSCD
OSCD
OSCD
OSCD
OSCD (1)
OSCD (1)
—
—
(1)
(1)
(1)
(1)
POR
Preliminary
Startup Timer
Oscillator
T
T
T
T
OST
OST
OST
OST (2)
—
—
—
—
—
2.
3.
4.
5.
6.
(2)
(2)
(2)
BOR Reset: The on-chip voltage regulator has
a BOR circuit that keeps the device in Reset
until V
delay, T
ensures that the voltage regulator output
becomes stable.
PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
for a specific period of time (T
BOR. The delay T
power
appropriate level for full-speed operation. After
the delay, T
becomes inactive, which in turn enables the
selected oscillator to start generating clock
cycles.
Oscillator Delay: The total delay for the clock to
be ready for various clock source selections is
given
“Oscillator Configuration” for more information.
When the oscillator clock is ready, the processor
begins execution from location 0x000000. The
user application programs a GOTO instruction at
the Reset address, which redirects program
execution to the appropriate start-up routine.
The Fail-Safe Clock Monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay, T
elapsed.
DD
in
BOR
PLL Lock Time
supplies
crosses the V
Table 6-1.
, has elapsed. The delay, T
T
T
T
T
PWRT
LOCK
LOCK
LOCK (3)
LOCK (3)
—
—
—
—
—
PWRT
, has elapsed, the SYSRST
(3)
(3)
© 2009 Microchip Technology Inc.
have
ensures that the system
Refer
BOR
OST
stabilized
T
threshold and the
T
T
OSCD
= 102.4 μs for a
T
T
OSCD
OSCD
to
OSCD
OSCD
Total Delay
T
T
PWRT
T
LOCK
LOCK (1,2,3)
T
T
OSCD (1)
OSCD (1)
LOCK (3)
Section 8.0
+ T
+ T
+ T
—
+ T
+ T
) after a
(1,2,3)
LOCK
at
OST
OST
OST
OST
FSCM
BOR
(1,2)
(1,2)
the
(1,3)
+
+
,
,