DSPIC30F3011-30I/PT Microchip Technology, DSPIC30F3011-30I/PT Datasheet - Page 101

• Manufacturer Part Number: DSPIC30F3011-30I/PT
• Description: IC DSPIC MCU/DSP 24K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Data Ram Size: 1024 B
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011, DM300018
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301130IPT

15.3
Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running or
Single-Shot mode. For edge-aligned PWM outputs, the
output has a period specified by the value in PTPER
and a duty cycle specified by the appropriate Duty Cycle
register, as shown in
driven active at the beginning of the period (PTMR = 0)
and is driven inactive when the value in the Duty Cycle
register matches PTMR.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is greater
than the value held in the PTPER register.
FIGURE 15-2:
15.4
Center-aligned PWM signals are produced by the
module when the PWM time base is configured in a
Continuous Up/Down Count mode, as shown in
Figure
The PWM compare output is driven to the active state
when the value of the Duty Cycle register matches the
value of PTMR and the PWM time base is counting
downwards (PTDIR = 1). The PWM compare output is
driven to the inactive state when the PWM time base is
counting upwards (PTDIR = 0) and the value in the
PTMR register matches the duty cycle value.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is equal to
the value held in the PTPER register.
© 2010 Microchip Technology Inc.
PTPER
0
15-3.
Edge-Aligned PWM
Center-Aligned PWM
Duty Cycle
PTMR
Value
Period
Figure
EDGE-ALIGNED PWM
New Duty Cycle Latched
15-2. The PWM output is
FIGURE 15-3:
15.5
There are three 16-bit Special Function Registers
(PDC1, PDC2 and PDC3) used to specify duty cycle
values for the PWM module.
The value in each Duty Cycle register determines the
amount of time that the PWM output is in the active
state. The Duty Cycle registers are 16 bits wide. The
LSb of a Duty Cycle register determines whether the
PWM edge occurs in the beginning. Thus, the PWM
resolution is effectively doubled.
15.5.1
The three PWM Duty Cycle registers are double-
buffered to allow glitchless updates of the PWM
outputs. For each duty cycle, there is a Duty Cycle reg-
ister that is accessible by the user and a second Duty
Cycle register that holds the actual compare value
used in the present PWM period.
For edge-aligned PWM output, a new duty cycle value
will be updated whenever a match with the PTPER
register occurs and PTMR is reset. The contents of the
duty cycle buffers are automatically loaded into the
Duty Cycle registers when the PWM time base is
disabled (PTEN = 0) and the UDIS bit is cleared in
PWMCON2.
When the PWM time base is in the Continuous Up/
Down Count mode, new duty cycle values are updated
when the value of the PTMR register is zero and the
PWM time base begins to count upwards. The contents
of the duty cycle buffers are automatically loaded into
the Duty Cycle registers when the PWM time base is
disabled (PTEN = 0).
PTPER
Duty
Cycle
dsPIC30F3010/3011
0
PWM Duty Cycle Comparison
Units
DUTY CYCLE REGISTER BUFFERS
Period/2
CENTER-ALIGNED PWM
Period
DS70141F-page 101
PTMR
Value