DSPIC30F3011-30I/PT Microchip Technology, DSPIC30F3011-30I/PT Datasheet - Page 146

• Manufacturer Part Number: DSPIC30F3011-30I/PT
• Description: IC DSPIC MCU/DSP 24K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Data Ram Size: 1024 B
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011, DM300018
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301130IPT

dsPIC30F3010/3011
20.3
The dsPIC30F3010/3011 differentiates between various
kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in
are used in software to determine the nature of the
Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
FIGURE 20-2:
DS70141F-page 146
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset cause by trap lockup (TRAPR)
Reset caused by illegal opcode, or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
MCLR
V
20-2.
Illegal Opcode/
Uninitialized W Register
DD
Reset
Instruction
RESET
TRAP Conflict
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
BOREN
Glitch Filter
Table
Digital
POR
20-5. These bits
BOR
20.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally
characteristics must meet specified starting voltage
and rise rate requirements. The POR pulse will reset a
POR timer and place the device in the Reset state. The
POR also selects the device clock source identified by
the oscillator configuration fuses.
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user-selected
power-up time-out (T
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
delay is at device power-up T
these delays have expired, SYSRST will be negated on
the next leading edge of the Q1 clock, and the PC will
jump to the Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3
DD
POR: POWER-ON RESET
through
rise is detected. The Reset pulse will occur
1.85V.
Figure
The
S
R
PWRT
© 2010 Microchip Technology Inc.
20-5.
) is applied. The T
device
Q
POR
+ T
supply
POR
POR
SYSRST
PWRT
), which is
, which is
. When
voltage
PWRT