DSPIC30F3011-30I/PT Microchip Technology, DSPIC30F3011-30I/PT Datasheet - Page 48

IC DSPIC MCU/DSP 24K 44TQFP

DSPIC30F3011-30I/PT

Manufacturer Part Number
DSPIC30F3011-30I/PT
Description
IC DSPIC MCU/DSP 24K 44TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/PT

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Data Ram Size
1024 B
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011, DM300018
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F301130IPT

Available stocks

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Quantity
Price
Part Number:
DSPIC30F3011-30I/PT
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0
dsPIC30F3010/3011
Address Error Trap:
This trap is initiated when any of the following
circumstances occurs:
1.
2.
3.
4.
5.
6.
Stack Error Trap:
This trap is initiated under the following conditions:
1.
2.
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
DS70141F-page 48
Note:
A misaligned data word access is attempted.
A data fetch from our unimplemented data
memory location is attempted.
A data access of an unimplemented program
memory location is attempted.
An instruction fetch from vector space is
attempted.
Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
The Stack Pointer is loaded with a value which
is greater than the (user-programmable) limit
value written into the SPLIM register (stack
overflow).
The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
5.3.2
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in
which may require the user to check if other traps are
pending, in order to completely correct the Fault.
‘Soft’ traps include exceptions of priority Level 8
through Level 11, inclusive. The arithmetic error trap
(Level 11) falls into this category of traps.
‘Hard’ traps include exceptions of priority Level 12
through Level 15, inclusive. The address error
(Level 12), stack error (Level 13) and oscillator error
(Level 14) traps fall into this category.
Each hard trap that occurs must be Acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, Acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically reset in a hard trap conflict
condition. The TRAPR status bit (RCON<15>) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 5-1:
AIVT
IVT
HARD AND SOFT TRAPS
Oscillator Fail Trap Vector
Address Error Trap Vector
Oscillator Fail Trap Vector
Address Error Trap Vector
Reset – GOTO Instruction
Stack Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Math Error Trap Vector
Reset – GOTO Address
Interrupt 52 Vector
Interrupt 52 Vector
Interrupt 53 Vector
Interrupt 53 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Interrupt 0 Vector
Interrupt 1 Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
Reserved Vector
TRAP VECTORS
© 2010 Microchip Technology Inc.
Reserved
Reserved
Reserved
Reserved
Figure 5-2
is implemented,
0x0000FE
0x000000
0x000004
0x000014
0x000094
0x000002
0x00007E
0x000082
0x000084
0x000080

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