DSPIC30F3011-20I/PT Microchip Technology, DSPIC30F3011-20I/PT Datasheet
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DSPIC30F3011-20I/PT Summary of contents
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... Microchip Technology Inc. dsPIC30F3010/3011 High-Performance, 16-Bit Digital Signal Controllers Data Sheet DS70141F ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Logic • 17-bit x 17-bit Single-Cycle Hardware Fractional/ Integer Multiplier • All DSP Instructions Single Cycle • ±16-bit Single-Cycle Shift © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Peripheral Features: • High-Current Sink/Source I/O Pins: 25 mA/25 mA • Timer module with Programmable Prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...
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... Program SRAM Device Pins Mem. Bytes/ Bytes Instructions dsPIC30F3010 28 24K/8K 1024 dsPIC30F3011 40/44 24K/8K 1024 DS70141F-page 4 CMOS Technology: • Low-Power, High-Speed Flash Technology • Wide Operating Voltage Range (2.5V to 5.5V) • Industrial and Extended Temperature Ranges • Low Power Consumption Output ...
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... REF EMUC3/AN1/V REF AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 40-Pin PDIP EMUD3/AN0/V REF EMUC3/AN1/V AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 FLTA/INT0/RE8 EMUD2/OC2/IC2/INT2/RD1 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 MCLR +/CN2/RB0 -/CN3/RB1 3 26 PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 6 23 ...
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... Pin Diagrams (Continued) (1) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70141F-page dsPIC30F3010 OSC2/CLKO/RC15 OSC1/CLKI AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 externally. SS © 2010 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 44-Pin TQFP PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 RF1 RF0 V V PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 32 2 OSC2/CLKO/RC15 31 3 OSC1/CLKI dsPIC30F3011 6 AN8/RB8 AN7/RB7 26 8 AN6/OCFA/RB6 9 25 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 DS70141F-page 7 ...
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... Pin Diagrams (Continued) (1) 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70141F-page RF1 5 29 RF0 6 dsPIC30F3011 OSC2/CLKO/RC15 OSC1/CLKI AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 externally ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com © 2010 Microchip Technology Inc. dsPIC30F3010/3011 to receive the most current information on all of our products. DS70141F-page 9 ...
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... NOTES: DS70141F-page 10 © 2010 Microchip Technology Inc. ...
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... The devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture. Figure 1-2 illustrate device block diagrams for the dsPIC30F3011 and dsPIC30F3010 devices. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Manual” dsPIC30F Figure 1-1 and ...
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... FIGURE 1-1: dsPIC30F3011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH PCL Program Counter Loop Stack Address Latch Control Control Logic Logic Program Memory (24 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...
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... OSC1/CLKI Generation Oscillator Start-up Timer POR/BOR Reset MCLR Watchdog Timer Input 10-bit ADC Capture Module SPI Timers QEI © 2010 Microchip Technology Inc. dsPIC30F3010/3011 X Data Bus Data Latch Data Latch Y Data X Data 16 RAM RAM (4 Kbytes) (4 Kbytes) Address Address Latch Latch RAGU ...
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... Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-1: dsPIC30F3011 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type ...
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... TABLE 1-1: dsPIC30F3011 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB8 I/O ST RC13-RC15 I/O ST RD0-RD3 I/O ST RE0-RE5, I/O ST RE8 RF0-RF6 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SS1 I ST ...
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... PWM3 Low output. PWM3 High output. Master Clear (Reset) input or programming voltage input. This pin is an active low Reset to the device. Compare Fault A input (for Compare channels and 4). Compare outputs 1 and 2. Analog = Analog input Output Power © 2010 Microchip Technology Inc. ...
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... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ...
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... NOTES: DS70141F-page 18 © 2010 Microchip Technology Inc. ...
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... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions ...
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... The upper byte of the SR register contains the DSP adder/subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. for SR layout. © 2010 Microchip Technology Inc. ...
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... Registers AD39 DSP ACCA Accumulators ACCB PC22 TBLPAG Data Table Page Address PSVPAG OAB SAB DA SRH © 2010 Microchip Technology Inc. dsPIC30F3010/3011 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 0 Program Space Visibility Page Address ...
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... Unsigned divide: Wm/Wn → W0; Rem → block diagram of the DSP engine is shown in Figure 2-2. TABLE 2-2: Instruction CLR ED EDAC MAC MOVSAC MPY MPY.N MSC selection DSP INSTRUCTION SUMMARY Algebraic Operation – – • change • – x • – x • y © 2010 Microchip Technology Inc. ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2010 Microchip Technology Inc. dsPIC30F3010/3011 40-Bit Accumulator A 40-Bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-Bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70141F-page 23 ...
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... OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to allows the user to take immediate action, for example, to correct system gain. Section 5.0 “Interrupts”) is set. This © 2010 Microchip Technology Inc. ...
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... No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 2.4.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY ...
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... The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. © 2010 Microchip Technology Inc. ...
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... TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, read/write instructions, bit 23 allows access to the Device ID, the User ID and the Configuration bits; otherwise, bit 23 is always clear. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 3-1: Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Manual” ...
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... Note: Program Space Visibility cannot be used to access bits<23:16> word in program memory. DS70141F-page 28 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> 0 PSVPAG<7:0> 23 bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA <15:0> Data EA <15:0> Data EA <14:0> 0 Byte Select © 2010 Microchip Technology Inc. ...
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... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2010 Microchip Technology Inc. dsPIC30F3010/3011 A set of table instructions are provided to move byte or word-sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address ...
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... Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle space addresses. The © 2010 Microchip Technology Inc. ...
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... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Program Space 0x0000 (1) PSVPAG ...
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... Optionally Mapped into Program Memory 0xFFFF DS70141F-page 32 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0xBFE 0x0C00 0x8000 X Data Unimplemented (X) 0xFFFE 3072 Bytes Near Data Space © 2010 Microchip Technology Inc. ...
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... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA Using any W © 2010 Microchip Technology Inc. dsPIC30F3010/3011 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read-Only ...
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... Fault. FIGURE 3-8: MSB 15 0001 Byte 1 0x0000 Byte 3 0003 0x0000 Byte 5 0005 0x0000 ® DATA ALIGNMENT LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2010 Microchip Technology Inc. ...
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... Note push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 ...
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... NOTES: DS70141F-page 38 © 2010 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2010 Microchip Technology Inc. dsPIC30F3010/3011 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode, (i.e., address boundary checks will be performed on both the lower and upper address boundaries). © 2010 Microchip Technology Inc. ...
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... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2010 Microchip Technology Inc. dsPIC30F3010/3011 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register MODCON<15:0> contains enable flags, as well register field to specify the W address registers ...
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... W register that has been designated as the Bit-Reversed Pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer N bytes, should not be enabled to do this, Bit-Reversed © 2010 Microchip Technology Inc. ...
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... TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 512 256 128 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Decimal XB<14:0> Bit-Reversed Address Modifier Value Bit-Reversed Address A0 Decimal 0x0100 0x0080 0x0040 ...
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... NOTES: DS70141F-page 44 © 2010 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS Register (SR) in the processor core. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the control and status flags for the processor exceptions ...
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... Reserved 39 47 PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA – PWM Fault Reserved 45-53 53-61 Reserved Lowest Natural Order Priority Note 1: Available on dsPIC30F3011 only © 2010 Microchip Technology Inc. (1) (1) (1) (1) ...
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... A momentary dip in the power supply to the device has been detected, which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 5.3 Traps Traps can be considered as non-maskable interrupts, indicating a software or hardware error, which adhere ...
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... Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector © 2010 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 0x00007E 0x000080 0x000082 0x000084 0x000094 0x0000FE ...
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... The RETFIE (Return from Interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 5.5 Alternate Vector Table In program memory, the Interrupt Vector Table (IVT) is ...
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TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2010 Microchip Technology Inc. dsPIC30F3010/3011 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Operations” Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Section 6.6 “Programming for further details. © 2010 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2010 Microchip Technology Inc. dsPIC30F3010/3011 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2010 Microchip Technology Inc. ...
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TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
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... NOTES: DS70141F-page 56 © 2010 Microchip Technology Inc. ...
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... A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires complete, but the write time will vary with voltage and temperature. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- ...
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... Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2010 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence, and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. © 2010 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR PORT Read LAT Read PORT © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins, and writes to the port pins, write the latch (LATx). Any bit and its associated data and control registers that are not valid for a particular device will be disabled ...
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... Typically this instruction would be a NOP will be OL EXAMPLE 8-1: MOV 0xFF00, W0 MOV W0, TRISBB NOP BTSS PORTB, #13 I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; Configure PORTB<15:8> inputs ; and PORTB<7:0> as outputs ; Delay 1 cycle ; Next Instruction © 2010 Microchip Technology Inc. ...
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... TABLE 8-1: dsPIC30F3011 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CA — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 — PORTC 02CE RC15 RC14 RC13 — ...
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TABLE 8-2: dsPIC30F3010 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CB — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 ...
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... CNEN1 00C0 CN7IE CN6IE CN5IE CNPU1 00C4 CN7PUE CN6PUE CN5PUE Note 1: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 for CN pin Bit 5 Bit 4 Bit 3 Bit 2 CN4IE CN3IE CN2IE CN4PUE CN3PUE CN2PUE ...
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... NOTES: DS70141F-page 66 © 2010 Microchip Technology Inc. ...
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... Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal © 2010 Microchip Technology Inc. dsPIC30F3010/3011 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. presents a block diagram of the 16-bit timer module. ...
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... Period register and be reset to 0x0000. When a match between the timer and the Period register occurs, an interrupt can be generated, if the respective timer interrupt enable bit is asserted. TSYNC Sync 1 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2010 Microchip Technology Inc. ...
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... XTAL SOSCO pF 100K © 2010 Microchip Technology Inc. dsPIC30F3010/3011 9.5.1 RTC OSCILLATOR OPERATION When the TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscillator output signal the value specified in the Period register, and is then reset to ‘0’. ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note ...
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... Interrupt on a 32-Bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 For 32-bit timer/counter operation, Timer2 is the lsw and Timer3 is the msw of the 32-bit timer. ...
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... Timer Configuration bit, T32 T2CON(<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70141F-page 72 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 X Gate 0 1 Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2010 Microchip Technology Inc. ...
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... T3IF Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer3. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2010 Microchip Technology Inc. dsPIC30F3010/3011 PR2 TMR2 Q D TGATE Q CK ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T3IE (IEC0<7>). © 2010 Microchip Technology Inc. ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — Legend: u ...
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... NOTES: DS70141F-page 76 © 2010 Microchip Technology Inc. ...
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... T4CON register. The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The Timer4/5 module is similar in operation to the Timer2/3 module. ...
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... The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) DS70141F-page 78 PR4 TMR4 Q D TGATE Q CK TON 1 x Gate Sync Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2010 Microchip Technology Inc. ...
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... Event Flag 1 TGATE Note: The dsPIC30F3010/3011 devices do not have external pin inputs to Timer4 or Timer5. In these devices, the following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (Gated Time Accumulation) © 2010 Microchip Technology Inc. dsPIC30F3010/3011 PR5 Comparator x 16 TMR5 Q D TGATE ...
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TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
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... ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels, 1 through N. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The key operational features of the input capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...
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... The capture module must be configured for interrupt only on the rising edge (ICM<2:0> = 111) in order for the input capture module to be used while the device is in Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. © 2010 Microchip Technology Inc. ...
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... ICSIDL bit must be asserted to a logic ‘0’. If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt based upon the selected number of capture events ...
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TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC7BUF 0158 IC7CON 015A — — ICSIDL ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1 through N. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits © 2010 Microchip Technology Inc. ...
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... Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS TMR3 = Duty Cycle (OCxR) © 2010 Microchip Technology Inc. dsPIC30F3010/3011 When the selected TMRx is equal to its respective Period register, PRx, the following four events occur on the next increment cycle: • TMRx is cleared. ...
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... IFS0 register, and must be cleared in software. The interrupt is enabled via the respective Timer Interrupt Enable bit (T2IE or T3IE), located in the IEC0 register. The output compare interrupt flag is never set during the PWM mode of operation. © 2010 Microchip Technology Inc. ...
Page 89
TABLE 13-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — (2) ...
Page 90
... NOTES: DS70141F-page 90 © 2010 Microchip Technology Inc. ...
Page 91
... INDX Digital Filter 3 Note 1: In dsPIC30F3010/3011, the UPDN pin is not available. Up/Down logic bit can still be polled by software. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...
Page 92
... UPDN signal is supplied to a SFR bit, UPDN (QEICON<11>), as a read-only bit. Note: QEI pins are multiplexed with analog inputs. The user must insure that all QEI associated pins are set as digital inputs in the ADPCFG register. © 2010 Microchip Technology Inc. ...
Page 93
... CY To enable the filter output for channels, QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 14.5 Alternate 16-Bit Timer/Counter When the QEI module is not configured for the QEI mode, QEIM< ...
Page 94
... The QEI Interrupt Flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 register. Enabling an interrupt is accomplished through the respective enable bit, QEIIE. The QEIIE bit is located in the IEC2 register. © 2010 Microchip Technology Inc. ...
Page 95
TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN DFLTCON 0124 — — — — POSCNT 0126 MAXCNT 0128 ADPCFG 02A8 — — ...
Page 96
... NOTES: DS70141F-page 96 © 2010 Microchip Technology Inc. ...
Page 97
... Uninterruptible Power Supply (UPS) The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution © 2010 Microchip Technology Inc. dsPIC30F3010/3011 • ‘On-the-Fly’ PWM frequency changes • Edge and Center-Aligned Output modes • ...
Page 98
... Generator and Override Logic PWM Channel 2 Dead-Time Generator 2 Generator and Override Logic PWM Channel 1 Dead-Time Generator 1 Generator and Override Logic Special Event Postscaler PTDIR PWM3H PWM3L PWM2H Output PWM2L Driver Block PWM1H PWM1L FLTA Special Event Trigger © 2010 Microchip Technology Inc. ...
Page 99
... Commutative Motors (ECMs). The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 15.1.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period register (PTPER) is matched ...
Page 100
... COUNTING MODE) • • • (PTPER + 1) PTMR Prescale Value T CY PWM The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined using Equation 15-3: EQUATION 15-3: PWM RESOLUTION • log ( PWM Resolution = log (2) © 2010 Microchip Technology Inc. using ) CY ...
Page 101
... PWM period. In addition, the out- put on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to the value held in the PTPER register. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 FIGURE 15-3: CENTER-ALIGNED PWM ...
Page 102
... On a load of the down timer due to a duty cycle comparison edge event. • write to the DTCON1 register. • On any device Reset. Note: The user should not modify the DTCON1 value while the PWM module is operating (PTEN = 1). Unexpected results may occur. © 2010 Microchip Technology Inc. 15-4, each ) may be CY ...
Page 103
... PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared and an interrupt is generated. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Dead Time 15.10 PWM Output Override The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units ...
Page 104
... PWM outputs return to normal operation at the beginning of the following PWM cycle or half-cycle boundary. The operating mode for the Fault input pin is selected using the FLTAM control bit in the FLTACON Special Function Register. The Fault pin can be controlled manually in software. © 2010 Microchip Technology Inc. ...
Page 105
... SEVTDIR bit is set, the Special Event Trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for a Continuous Up/Down Count mode. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 15.14.1 SPECIAL EVENT TRIGGER POSTSCALER The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio ...
Page 106
TABLE 15-1: PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PWMCON2 01CA ...
Page 107
... If any trans- mit data has been written to the buffer register, the © 2010 Microchip Technology Inc. dsPIC30F3010/3011 contents of the transmit buffer are moved to SPI1SR. The received data is thus placed in SPI1BUF and the transmit data in SPI1SR is ready for the next transfer ...
Page 108
... Clock Edge Control Select Enable Master Clock SDOx SDIy SDIx SDOy LSb Serial Clock SCKx SCKy Secondary Primary F Prescaler Prescaler CY 1:1 – 1 16, 64 SPI Slave Serial Input Buffer (SPIyBUF) Shift Register (SPIySR) MSb LSb PROCESSOR 2 © 2010 Microchip Technology Inc. ...
Page 109
... Therefore, when the SS1 pin is asserted low again, transmission/reception will begin at the MSb, even if SS1 has been deasserted in the middle of a transmit/receive. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down ...
Page 110
TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend: — = unimplemented bit, ...
Page 111
... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 17.1.1 VARIOUS I The following types • Slave operation with 7-bit addressing 2 • Slave operation with 10-bit addressing 2 • ...
Page 112
... LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2010 Microchip Technology Inc. ...
Page 113
... SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 114
... C bus have deasserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2010 Microchip Technology Inc. ...
Page 115
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device-specific general call address. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 2 17. Master Support As a master device, six operations are supported: ...
Page 116
... C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle master event Interrupt Service 2 C bus is free (i.e., the P bit is set), the 2 C bus © 2010 Microchip Technology Inc. ...
Page 117
TABLE 17-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN ...
Page 118
... NOTES: DS70141F-page 118 © 2010 Microchip Technology Inc. ...
Page 119
... UTXBRK Data UxTX Parity Note dsPIC30F3010 only has UART1. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 18.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 120
... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxMODE UxSTA Control Signals UxRXIF © 2010 Microchip Technology Inc. ...
Page 121
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity, 1 Stop bit (typically represented 1). © 2010 Microchip Technology Inc. dsPIC30F3010/3011 18.3 Transmitting Data 18.3.1 ...
Page 122
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. RXB) X © 2010 Microchip Technology Inc. ...
Page 123
... FERR bit set. The Break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 124
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2010 Microchip Technology Inc. ...
Page 125
TABLE 18-1: UART1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 U1MODE 020C UARTEN — USIDL — U1STA 020E UTXISEL — — — UTXBRK UTXEN U1TXREG 0210 — — — — U1RXREG ...
Page 126
... NOTES: DS70141F-page 126 © 2010 Microchip Technology Inc. ...
Page 127
... The ADC has a unique feature of REF REF being able to operate while the device is in Sleep mode. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • ...
Page 128
... AN1 Note 1: Not available on dsPIC30F3010 devices. DS70141F-page 128 + CH1 ADC S/H - 10-Bit Result + CH2 S/H - 16-word, 10-bit Dual Port + CH3 S/H CH1,CH2, - CH3,CH0 Sample/Sequence Sample Input Switches + CH0 S/H - © 2010 Microchip Technology Inc. Conversion Logic Buffer Control Input Mux Control ...
Page 129
... The channels are then converted sequentially. Obvi- ously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 The CHPS bits select how many channels are sam- pled. This can vary from channels. If the CHPS bits select 1 channel, the CH0 channel will be sampled at the sample clock and converted ...
Page 130
... ADCS<5:0> – time AD = 5V). Refer to Section 23.0 DD for minimum T under AD shows a sample calculation for the A/D CONVERSION CLOCK CALCULATION T = 154 nsec nsec (30 MIPS – 154 nsec = 2 • – nsec = 8. (ADCS<5:0> nsec = ( 165 nsec © 2010 Microchip Technology Inc. ...
Page 131
... Up to 256. 5.0 kΩ AD 300 ksps Note 1: External V - and V + pins must be used for correct operation. See Figure 19-2 for recommended REF REF circuit. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Table 19-1 Max V Temperature S DD 500Ω 4.5V -40°C to +85°C to 5.5V ANx 500Ω ...
Page 132
... The analog input multiplexer must be configured so that the same input pin is connected to both sample and hold channels. The ADC converts the value held on one S/H channel, while the second S/H channel acquires a new input sample. DS70141F-page 132 dsPIC30F3011 ...
Page 133
... ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time writing: SAMC<4:0> = 00010 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 19.7.3 600 ksps CONFIGURATION GUIDELINE The configuration for 600 ksps operation is dependent on whether a single input pin sampled or whether multiple pins will be sampled ...
Page 134
... Section 23.0 “Electrical Characteristics” sample time requirements source V DD ≤ 250Ω Sampling Switch LEAKAGE V = 0.6V T ± 500 nA negligible if Rs ≤ 5 kΩ. PIN period of sampling AD for T and AD ≤ 3 kΩ HOLD = DAC capacitance = 4 © 2010 Microchip Technology Inc. ...
Page 135
... Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 © 2010 Microchip Technology Inc. dsPIC30F3010/3011 If the ADC interrupt is enabled, the device will wake-up from Sleep. If the ADC interrupt is not enabled, the ADC module will then be turned off, although the ADON bit will remain set ...
Page 136
... Any external components connected (via high-impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. and V as ESD the input voltage exceeds this SS © 2010 Microchip Technology Inc. ...
Page 137
TABLE 19-2: ADC REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — ...
Page 138
... NOTES: DS70141F-page 138 © 2010 Microchip Technology Inc. ...
Page 139
... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 20.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 140
... RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70141F-page 140 Description (1) . (2) . (1) . (1) . (1) . (1) . (1) . (3) /4 output . OSC (3) . © 2010 Microchip Technology Inc. ...
Page 141
... FIGURE 20-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 TUN<3:0> 4 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2010 Microchip Technology Inc. dsPIC30F3010/3011 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Timer ...
Page 142
... OSC2 Function OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKO 1 1 CLKO OSC2 0 0 (Note (Note (Note © 2010 Microchip Technology Inc. ...
Page 143
... RC oscillator (nominal 7.37 MHz). The user can tune the FRC oscillator within a range of +10.5% © 2010 Microchip Technology Inc. dsPIC30F3010/3011 (840 kHz) and -12% (960 kHz) in steps of 1.50% around the factory calibrated setting, as shown in Table 20-4 ...
Page 144
... Note: The application should not attempt to switch to a clock of frequency lower than 100 kHz when the Fail-Safe Clock Monitor is enabled. If such clock switching is performed, the device may generate an oscillator fail trap and switch to the fast RC oscillator. © 2010 Microchip Technology Inc. ...
Page 145
... Byte Write 0x78 to OSCCON high Byte Write 0x9A to OSCCON high : Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 DS70141F-page 145 ...
Page 146
... Q1 clock, and the PC will jump to the Reset vector. The timing for the SYSRST signal is shown in 20-5. These bits Figure 20-3 through BOR ), which is POR The device supply voltage , which is POR ) is applied. The T PWRT PWRT + T . When POR PWRT Figure 20- SYSRST © 2010 Microchip Technology Inc. ...
Page 147
... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 20-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset © 2010 Microchip Technology Inc. dsPIC30F3010/3011 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE 1 ...
Page 148
... C, in the event of MCLR/V pin breakdown due to PP Electrostatic Discharge Electrical Overstress (EOS). Note: Dedicated supervisory devices, such as the MCP1XX and MCP8XX, may also be used as an external Power-on Reset circuit. © 2010 Microchip Technology Inc. = 100 μ POR FSCM powers DD (ESD) or ...
Page 149
... Trap Reset 0x000000 Illegal Operation Reset 0x000000 Legend unchanged unknown Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ...
Page 150
... In order to have the small- est possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected before entering Sleep and T delays POR LOCK PWRT (~ 10 μs) is applied. This is the smallest . PWRT delay and OST POR © 2010 Microchip Technology Inc. ...
Page 151
... Upon wake-up from Idle mode, the clock is re-applied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Any interrupt that is individually enabled (using the IE bit) and meets the prevailing priority level will be able to wake-up the processor ...
Page 152
... PGD and PGC pin functions in all dsPIC30F devices EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/ EMUC3 is selected as the debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions ( are not multiplexed with the PGD and PGC pin functions. © 2010 Microchip Technology Inc PGC ...
Page 153
TABLE 20-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST — — OSCCON 0742 — — COSC<1:0> — OSCTUN 0744 — — — — — Legend: ...
Page 154
... NOTES: DS70141F-page 154 © 2010 Microchip Technology Inc. ...
Page 155
... The File register specified by the value ‘f’ • The destination, which could either be the File register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 156
... Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “16-bit MCU and DSC Programmer’s Reference (DS70157). Description © 2010 Microchip Technology Inc. Manual” ...
Page 157
... Y data space Prefetch Address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space Prefetch Destination register for DSP instructions ∈ {W4..W7} Wyd © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Description DS70141F-page 157 ...
Page 158
... Branch if Accumulator A Overflow Branch if Accumulator B Overflow Branch if Overflow Branch if Accumulator A Saturated Branch if Accumulator B Saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2010 Microchip Technology Inc Status Flags cycle Affected OA,OB,SA, C,DC,N,OV,Z ...
Page 159
... CPSGT Wb CPSLT CPSLT Wb CPSNE CPSNE Wb DAW DAW Wn © 2010 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 160
... Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Multiply and Accumulate Square and Accumulate © 2010 Microchip Technology Inc Status Flags cycle Affected C,DC,N,OV,Z ...
Page 161
... Wn 59 RESET RESET 60 RETFIE RETFIE 61 RETLW RETLW #lit10,Wn 62 RETURN RETURN © 2010 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words Move Move Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) ...
Page 162
... WREG = WREG – – lit5 – WREG – f – (C) WREG = WREG – f – ( – Wb – ( lit5 – Wb – ( Nibble Swap Byte Swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> © 2010 Microchip Technology Inc Status Flags cycle Affected C,N C,N,Z ...
Page 163
... XOR XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd © 2010 Microchip Technology Inc. dsPIC30F3010/3011 # of Description words Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Status Flags cycle Affected ...
Page 164
... NOTES: DS70141F-page 164 © 2010 Microchip Technology Inc. ...
Page 165
... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2010 Microchip Technology Inc. dsPIC30F3010/3011 22.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 166
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2010 Microchip Technology Inc. ...
Page 167
... Microchip Technology Inc. dsPIC30F3010/3011 22.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...
Page 168
... This usually includes a single application and debug capability, all on one board. for DDMAX Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2010 Microchip Technology Inc. ...
Page 169
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 (except V and MCLR) (Note 1) ...
Page 170
... Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +150 °C -40 — +125 ° INT – T )/θ Typ Max Unit Notes 42 — °C — °C — °C — °C — °C/W 1 © 2010 Microchip Technology Inc. ...
Page 171
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min ...
Page 172
... OSC1 DD 0.128 MIPS LPRC (512 kHz) 1.8 MIPS FRC (7.37MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS . DD © 2010 Microchip Technology Inc. ...
Page 173
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2010 Microchip Technology Inc. dsPIC30F3010/3011 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 174
... PD Base Power-Down Current Watchdog Timer Current: ΔI (3) WDT Timer 1 w/32 kHz Crystal: ΔI ( BOR on: ΔI (3) BOR © 2010 Microchip Technology Inc. ...
Page 175
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 176
... Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Oscillator mode C™ mode (Device not in Brown-out Reset) © 2010 Microchip Technology Inc. ...
Page 177
... During Programming EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 178
... Section 23.1 "DC Characteristics". Load Condition 2 – for OSC2 Pin 464Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 ≤ +85°C for Industrial A ≤ +125°C for Extended OS31 OS31 OS41 © 2010 Microchip Technology Inc. ...
Page 179
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 180
... V = 4 ≤ +85° 3 ≤ +125° 3 ≤ +85° 4 ≤ +125° 4 ≤ +85° 3 ≤ +85° 4 ≤ +125° 4 © 2010 Microchip Technology Inc. ...
Page 181
... Oscillator T CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F © 2010 Microchip Technology Inc. dsPIC30F3010/3011 (3) (3) MIPS MIPS (2) (μsec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1.0 4.0 0.4 2.5 10.0 0.16 6.25 — ...
Page 182
... DD ≤ +85°C for Industrial ≤ +125°C for Extended Conditions ≤ +85° 3.0-5. ≤ +125° 3.0-5. ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions V = 5.0V, ±10 3.3V, ±10 2.5V DD © 2010 Microchip Technology Inc. ...
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... These parameters are asynchronous events not related to any internal clock edges. 2: Measurements are taken in RC mode and EC mode where CLKO output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 2 ...
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... Industrial A ≤ +125°C for Extended A Units Conditions μs -40°C to +85°C ms -40°C to +85° User programmable μs -40°C to +85°C μ 2. 3.3V, ±10 5V, ±10% DD μs ≤ (D034) DD BOR — OSC1 period OSC © 2010 Microchip Technology Inc. ...
Page 185
... Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) (2) ...
Page 186
... Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz 1.5 — © 2010 Microchip Technology Inc. ...
Page 187
... TxCK Low Time TC15 TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ Synchronous, 0 ...
Page 188
... Synchronous — CY with prescaler 0.5 T — CY TQ20 ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TQ15 — ns Must also meet parameter TQ15 — ns 1.5 T — CY © 2010 Microchip Technology Inc. ...
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... OC10 TccF OCx Output Fall Time OC11 TccR OCx Output Rise Time Note 1: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40° ...
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... DS70141F-page 190 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min Typ Max Units — — — — ns -40°C ≤ T ≤ +85°C for Industrial A -40°C ≤ T ≤ +125°C for Extended A Conditions © 2010 Microchip Technology Inc. ...
Page 191
... MP20 T FD I/O Change MP30 T Minimum Pulse Width FH Note 1: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 MP30 MP11 MP10 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 192
... T Operating temperature -40°C ≤ T (1) (2) Typ Max 6 T — — — — — — CY ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 16, 32, 64, 128 and 256 (Note 16, 32, 64, 128 and 256 (Note 2) © 2010 Microchip Technology Inc. ...
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... Alignment of index pulses to QEA and QEB is shown for position counter reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB), but index pulse recognition occurs on falling edge. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 TQ50 TQ55 Standard Operating Conditions: 2 ...
Page 194
... Industrial A -40°C ≤ T ≤ +125°C for Extended A Max Units Conditions — ns — ns — ns See parameter DO32 — ns See parameter DO31 — ns See parameter DO32 — ns See parameter DO31 30 ns — ns — ns © 2010 Microchip Technology Inc. ...
Page 195
... These parameters are characterized but not tested in manufacturing. 2: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 3: Assumes 50 pF load on all SPI pins. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 SP10 SP21 SP35 SP20 ...
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... SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) SP35 SDO X SDI SDI X SP40 Note: Refer to Figure 23-2 for load conditions. DS70141F-page 196 SP70 SP72 SP73 SP73 SP72 MSb BIT14 - - - - - -1 SP30,SP31 MSb In BIT14 - - - -1 SP41 SP52 LSb SP51 LSb In © 2010 Microchip Technology Inc. ...
Page 197
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 198
... SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SP30,SP31 SDI SDI X MSb In SP41 SP40 Note: Refer to Figure 23-2 for load conditions. DS70141F-page 198 SP70 SP72 SP73 SP35 SP73 SP72 SP52 BIT14 - - - - - -1 LSb BIT14 - - - -1 LSb In SP52 SP51 © 2010 Microchip Technology Inc. ...
Page 199
... The minimum clock period for SCx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2010 Microchip Technology Inc. dsPIC30F3010/3011 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 200
... C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 23-2 for load conditions. DS70141F-page 200 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 © 2010 Microchip Technology Inc. ...