DSPIC33FJ16GS504-I/PT Microchip Technology, DSPIC33FJ16GS504-I/PT Datasheet - Page 93

• Manufacturer Part Number: DSPIC33FJ16GS504-I/PT
• Description: IC DSPIC MCU/DSP 16K 44-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ16GS504-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 6-2:
© 2009 Microchip Technology Inc.
Oscillator Clock
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
Device Status
POR Reset
BOR Reset
SYSRST
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until V
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections is given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application
6: If the Fail-Safe Clock Monitor (FSCM) is enabled, it begins to monitor the system clock when the system clock is
FSCM
V
active until V
the V
becomes stable.
of time (T
appropriate level for full-speed operation. After the delay, T
inactive, which in turn, enables the selected oscillator to start generating clock cycles.
Table 6-1. Refer to Section 8.0 “Oscillator Configuration” for more information.
programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up
routine.
ready and the delay, T
DD
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
BOR
1
SYSTEM RESET TIMING
PWRT
threshold and the delay, T
DD
) after a BOR. The delay, T
2
crosses the V
T
FSCM
V
POR
POR
, has elapsed.
POR
threshold and the delay, T
BOR
, has elapsed. The delay, T
Preliminary
V
PWRT
BOR
T
, ensures that the system power supplies have stabilized at the
PWRT
T
3
BOR
Reset
Time
T
POR
OSCD
PWRT
, has elapsed.
BOR
has elapsed and the SYSRST becomes
, ensures the voltage regulator output
T
OST
4
T
LOCK
DS70318D-page 91
5
6
Run
DD
T
crosses
FSCM