DSPIC30F3010-30I/ML Microchip Technology, DSPIC30F3010-30I/ML Datasheet - Page 20
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DSPIC30F3010-30I/ML
Manufacturer Part Number
DSPIC30F3010-30I/ML
Description
IC DSPIC MCU/DSP 24K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F3010-30ISO.pdf
(228 pages)
2.DSPIC30F3010-30ISO.pdf
(18 pages)
3.DSPIC30F3010-30ISO.pdf
(6 pages)
4.DSPIC30F3010-30ISO.pdf
(16 pages)
5.DSPIC30F3010-30ISO.pdf
(22 pages)
Specifications of DSPIC30F3010-30I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Package
44QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
I2C/SPI/UART
On-chip Adc
6-chx10-bit
Number Of Timers
5
For Use With
XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFNXLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F301030IML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F3010-30I/ML
Manufacturer:
MICROCHI
Quantity:
20 000
dsPIC30F3010/3011
2.2
The programmer’s model is shown in
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (ACCA and ACCB),
STATUS Register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program Coun-
ter (PC). The working registers can act as Data,
Address or Offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a Shadow register asso-
ciated with each of them, as shown in Figure 2-1. The
Shadow register is used as a temporary holding regis-
ter and can transfer its contents to or from its host reg-
ister upon the occurrence of an event. None of the
Shadow registers are accessible directly. The following
rules apply for transfer of registers into and out of
shadows.
• PUSH.S and POP.S
• DO instruction
When a byte operation is performed on a working reg-
ister, only the Least Significant Byte (LSB) of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte-wide data memory space accesses.
DS70141F-page 20
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
Programmer’s Model
Figure 2-1
and
2.2.1
The dsPIC DSC devices contain a software stack. W15
is the dedicated Software Stack Pointer, and will be
automatically modified by exception processing and
subroutine calls and returns. However, W15 can be ref-
erenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
stack frames).
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
The dsPIC DSC core has a 16-bit STATUS Register
(SR), the LSB of which is referred to as the SR Low
Byte (SRL) and the MSB as the SR High Byte (SRH).
See
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Prior-
ity Level status bits, IPL<2:0>, and the Repeat Active
status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value which is then stacked.
The upper byte of the SR register contains the DSP
adder/subtracter status bits, the DO Loop Active bit
(DA) and the Digit Carry (DC) status bit.
2.2.3
The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
Note:
Figure 2-1
SOFTWARE STACK POINTER/
FRAME POINTER
In order to protect against misaligned
stack accesses, W15<0> is always clear.
STATUS REGISTER
PROGRAM COUNTER
for SR layout.
© 2010 Microchip Technology Inc.