DSPIC33FJ128GP202-I/MM Microchip Technology, DSPIC33FJ128GP202-I/MM Datasheet
DSPIC33FJ128GP202-I/MM
Specifications of DSPIC33FJ128GP202-I/MM
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DSPIC33FJ128GP202-I/MM Summary of contents
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... Microchip Technology Inc. High-Performance, 16-bit Digital Signal Controllers Data Sheet DS70292E ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA © 2011 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Timers/Capture/Compare/PWM: • Timer/Counters five 16-bit timers: ...
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... Programmable bit length for the CRC generator polynomial (up to 16-bit length) - 8-deep, 16-bit or 16-deep, 8-bit FIFO for data input Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin TQFP/QFN Note: See the device variant tables for exact peripheral features per device. © 2011 Microchip Technology Inc. ...
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... The device names, pin counts, memory sizes, and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 CONTROLLER FAMILIES Device dsPIC33FJ128GP804 44 128 16 26 dsPIC33FJ128GP802 28 128 16 16 dsPIC33FJ128GP204 44 128 8 26 dsPIC33FJ128GP202 28 128 8 16 dsPIC33FJ64GP804 dsPIC33FJ64GP802 dsPIC33FJ64GP204 dsPIC33FJ64GP202 28 ...
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... PGEC3/ASCL1/RP6 14 15 Table 1 in this section for the list of available peripherals. = Pins are tolerant (1) /CN11/PMCS1/RB15 (1) /CN12/PMWR/RB14 (1) /CN13/PMRD/RB13 (1) /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 (1) /CN21/PMD3/RB9 (1) /CN22/PMD4/RB8 (1) /CN24/PMD6/RB6 = Pins are tolerant /CN11/PMCS1/RB15 (1) /CN12/PMWR/RB14 /CN13/PMRD/RB13 /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 (1) /CN21/PMD3/RB9 (1) /CN22/PMD4/RB8 (1) /CN24/PMD6/RB6 © 2011 Microchip Technology Inc. ...
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... AN5/C1IN+/RP3 /CN7/RB3 V OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3 Note 1: The RPx pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2011 Microchip Technology Inc. AN11/DAC1RN/RP13 1 21 AN12/DAC1RP/RP12 2 20 PGEC2/TMS/RP11 3 ...
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... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70292E-page 8 AN11/ RP13 1 21 AN12/ RP12 2 20 dsPIC33FJ32GP302 3 PGEC2/TMS/RP11 19 dsPIC33FJ64GP202 4 PGED2/TDI/RP10 18 dsPIC33FJ128GP202 CAP TDO/SDA1/RP9 Table 1 in this section for the list of available peripherals. = Pins are tolerant ...
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... OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2011 Microchip Technology Inc. AN11/DAC1RN/RP13 11 23 AN12/DAC1RP/RP12 24 10 PGEC2/RP11 25 9 ...
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... CAP dsPIC33FJ64GP204 (1) RP25 29 5 dsPIC33FJ128GP204 (1) RP24 30 4 (1) RP23 31 3 (1) RP22 32 2 SDA1/RP9 33 1 Table 1 in this section for the list of available peripherals. = Pins are tolerant (1) /CN13/PMRD/RB13 (1) /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 /CN19/PMA6/RC9 /CN20/PMA5/RC8 /CN17/PMA0/RC7 /CN18/PMA1/RC6 (1) /CN21/PMD3/RB9 externally. SS © 2011 Microchip Technology Inc. ...
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... AN5/C1IN+/RP3 /CN7/RB3 (1) AN6/DAC1RM/RP16 /CN8/RC0 (1) AN7/DAC1LM/RP17/ /CN9/RC1 (1) AN8/CV /RP18 /PMA2/CN10/RC2 REF OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See © 2011 Microchip Technology Inc. 11 AN11/DAC1RN/RP13 AN12/DAC1RP/RP12 25 9 PGEC2/RP11 8 26 PGED2/EMCD2/RP10 dsPIC33FJ64GP804 CAP dsPIC33FJ128GP804 (1) 5 RP25 ...
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... PGED2/EMCD2/RP10 dsPIC33FJ32GP304 CAP 6 dsPIC33FJ64GP204 ( RP25 /CN19/PMA6/RC9 dsPIC33FJ128GP204 (1) 4 RP24 /CN20/PMA5/RC8 30 (1) 3 RP23 /CN17/PMA0/RC7 31 (1) 2 RP22 /CN18/PMA1/RC6 32 1 SDA1/RP9 33 Table 1 in this section for the list of available peripherals. = Pins are tolerant (1) /CN13/PMRD/RB13 (1) /CN14/PMD0/RB12 (1) /CN15/PMD1/RB11 (1) /CN16/PMD2/RB10 (1) /CN21/PMD3/RB9 © 2011 Microchip Technology Inc. ...
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... High Temperature Electrical Characteristics ............................................................................................................................ 375 32.0 Packaging Information.............................................................................................................................................................. 385 Appendix A: Revision History............................................................................................................................................................. 395 Index .................................................................................................................................................................................................. 403 The Microchip Web Site ..................................................................................................................................................................... 409 Customer Change Notification Service .............................................................................................................................................. 409 Customer Support .............................................................................................................................................................................. 409 Reader Response .............................................................................................................................................................................. 410 Product Identification System ............................................................................................................................................................ 411 © 2011 Microchip Technology Inc. DS70292E-page 13 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS70292E-page 14 to receive the most current information on all of our products. © 2011 Microchip Technology Inc. ...
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... Refer to “Memory Organization” sheet for device-specific register and bit information. © 2011 Microchip Technology Inc. This document contains device specific information for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Digital Signal Controller (DSC) Devices. The dsPIC33F devices ...
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... Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support MCLR Timers UART1, 2 ADC1 1-5 IC1 CNx I2C1 PORTA DMA RAM PORTB 16 DMA Controller PORTC Remappable Pins 16-bit ALU 16 OC/ PWM1-4 DCI © 2011 Microchip Technology Inc. ...
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... O — SS2 I/O ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer © 2011 Microchip Technology Inc. PPS Description Analog input channels. No External clock source input. Always associated with OSC1 pin function. No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Clock input pin for programming/debugging communication channel 3. No Master Clear (Reset) input. This pin is an active-low Reset to the device. No Positive supply for analog modules. This pin must be connected at all times. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input © 2011 Microchip Technology Inc. ...
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... Analog REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer © 2011 Microchip Technology Inc. PPS Description No Ground reference for analog modules. No Positive supply for peripheral logic and I/O pins. No CPU logic filter capacitor connection. ...
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... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 20 © 2011 Microchip Technology Inc. ...
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... ADC module is implemented Note: The AV and connected independent of the ADC voltage reference source. © 2011 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • ...
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... Ensure that the MCLR pin V and V specifications are met MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met © 2011 Microchip Technology Inc. is ...
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... REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2011 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “ ...
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... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor between V and the unused pin. DS70292E-page 24 SS © 2011 Microchip Technology Inc. ...
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... X04, and dsPIC33FJ128GPX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and © 2011 Microchip Technology Inc. a program (instruction) memory read per instruction cycle result, three parameter instructions can be supported, allowing operations to be executed in a single cycle ...
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... Data Latch PCH PCL X RAM Y RAM Address Address Loop Control Latch Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine W Register Array Divide Support DMA 16 RAM DMA Controller 16-bit ALU 16 To Peripheral Modules © 2011 Microchip Technology Inc. ...
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... Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH © 2011 Microchip Technology Inc. D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 PC0 0 Program Space Visibility Page Address ...
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... This bit can be read or cleared (not set). Clearing this bit clears SA and SB. DS70292E-page 28 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) (4) R/C R/W-0 (4) SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2011 Microchip Technology Inc. ...
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... Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15> This bit can be read or cleared (not set). Clearing this bit clears SA and SB. © 2011 Microchip Technology Inc. (2) DS70292E-page 29 ...
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... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70292E-page 30 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...
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... The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. © 2011 Microchip Technology Inc. 3.7 DSP Engine The DSP engine consists of a high-speed 17-bit x ...
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... AND dsPIC33FJ128GPX02/X04 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70292E-page 32 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2011 Microchip Technology Inc. ...
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... In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented. © 2011 Microchip Technology Inc. The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: • ...
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... Saturation”). For the MAC class of instructions, the accumulator write- back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2011 Microchip Technology Inc. saturation (see ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2011 Microchip Technology Inc. 3.7.4 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 36 © 2011 Microchip Technology Inc. ...
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... Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) Reserved Note: Memory areas are not shown to scale. © 2011 Microchip Technology Inc. 4.1 Program Address Space The program dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 and instructions. The space is addressable by a 24-bit families ...
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... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Table”. least significant word Instruction Width Section 7.1 “Interrupt Vector PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2011 Microchip Technology Inc. ...
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... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2011 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code ...
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... SFR Space 0x07FF 0x0801 X Data RAM (X) 0x0FFF 0x1001 Y Data RAM (Y) 0x13FF 0x1401 DMA RAM 0x17FF 0x1801 0x8001 X Data Unimplemented (X) LSB Address 0x0000 0x07FE 0x0800 6 Kbyte 0x0FFE Near 0x1000 Data Space 0x13FE 0x1400 0x17FE 0x1800 0x8000 0xFFFE © 2011 Microchip Technology Inc. ...
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... AND dsPIC33FJ128GPX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ128GP202/204 AND dsPIC33FJ64GP202/ 204 DEVICES WITH 8 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 8 Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © ...
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... Program Memory 0xFFFF DS70292E-page 42 LSB Address 16 bits MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE 0x4000 DMA RAM 0x47FE 0x4800 0x8000 X Data Unimplemented (X) 0xFFFE 8 Kbyte Near Data Space © 2011 Microchip Technology Inc. ...
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... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2011 Microchip Technology Inc. 4.2.6 DMA RAM Every dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ ...
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TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...
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... TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr 0060 CN15IE CN14IE CN13IE CN12IE CNEN1 0062 — CN30IE CN29IE — CNEN2 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU1 CNPU2 006A — ...
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TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF ...
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TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 4-7: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...
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TABLE 4-10: UART2 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U2MODE 0230 UARTEN — USIDL IREN U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — U2TXREG 0234 — — — — U2RXREG 0236 — — — ...
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... TABLE 4-13: ADC1 REGISTER MAP FOR dsPIC33FJ64GP202/802, dsPIC33FJ128GP202/802 AND dsPIC33FJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — — AD1CHS0 ...
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TABLE 4-16: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...
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TABLE 4-16: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...
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TABLE 4-17: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — ...
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TABLE 4-19: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 C1RXM0EID ...
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TABLE 4-19: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11EID 046E C1RXF12SID 0470 C1RXF12EID 0472 C1RXF13SID 0474 C1RXF13EID 0476 C1RXF14SID 0478 C1RXF14EID 047A C1RXF15SID 047C ...
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TABLE 4-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR4 0688 — — — ...
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... TABLE 4-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...
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... TABLE 4-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PMMODE 0602 BUSY IRQM<1:0> PMADDR ADDR15 CS1 0604 PMDOUT1 PMDOUT2 0606 PMDIN1 0608 PMPDIN2 060A PMAEN 060C — ...
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... C2EVT C1EVT CVRCON 0632 — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-29: PORTA REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — ...
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TABLE 4-30: PORTA REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA ...
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TABLE 4-33: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RCON 0740 TRAPR IOPUWR — — 0742 — COSC<2:0> OSCCON 0744 ROI DOZE<2:0> CLKDIV 0746 — — — — PLLFBD 0748 — — ...
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... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2011 Microchip Technology Inc. 4.2.8 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security ...
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... ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. MAC INSTRUCTIONS Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). OTHER INSTRUCTIONS © 2011 Microchip Technology Inc. ...
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... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2011 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes) ...
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... If Bit-Reversed Addressing has already been enabled by setting the BREN bit (XBREV<15>), a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, should not be enabled © 2011 Microchip Technology Inc. ...
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... TABLE 4-38: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2011 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Decimal ...
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... TBLPAG<7:0> 0xxx xxxx xxxx xxxx xxxx xxxx TBLPAG<7:0> 1xxx xxxx xxxx xxxx xxxx xxxx PSVPAG<7:0> xxxx xxxx © 2011 Microchip Technology Inc. show how the program EA is <14:1> <0> 0 xxxx xxx0 Data EA<15:0> Data EA<15:0> (1) Data EA<14:0> xxx xxxx xxxx xxxx ...
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... Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. © 2011 Microchip Technology Inc. Program Counter 0 23 bits ...
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... TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. Section 5.0 “Flash © 2011 Microchip Technology Inc. ...
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... PAG is mapped into the upper half of the data memory space... © 2011 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
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... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 72 © 2011 Microchip Technology Inc. ...
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... ADDRESSING FOR TABLE REGISTERS Using Program Counter Using 1/0 Table Instruction User/Configuration Space Select © 2011 Microchip Technology Inc. programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (V ), ground (V DD This allows customers to manufacture boards with and unprogrammed devices and then program the digital signal controller just before shipping the product ...
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... Equation 5-2. MINIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 1 0.00375 – Equation 5-3. MAXIMUM ROW WRITE TIME 11064 Cycles = × × 0.05 – 1 0.00375 – (Register 5-1) controls which 5- write-only register that is for © 2011 Microchip Technology Inc. ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2011 Microchip Technology Inc. (1) U-0 U-0 — — (1) U-0 R/W-0 — ...
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... NVMKEY<7:0>: Key Register (write-only) bits DS70292E-page 76 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2011 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit ...
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... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted © 2011 Microchip Technology Inc. ...
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... Regulator V DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2011 Microchip Technology Inc. A simplified block diagram of the Reset module is shown in Figure Any active source of reset will make the SYSRST sig- nal active. On system Reset, some of the registers and associated with the CPU and peripherals are forced to a known Reset state and some are unaffected ...
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... SWDTEN bit setting. DS70292E-page 80 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 81
... All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2011 Microchip Technology Inc. (1) (CONTINUED) DS70292E-page 81 ...
Page 82
... T T OST LOCK T T OST LOCK — T LOCK T — OST — — Total Delay T OSCD OSCD LOCK OSCD OST OSCD OST — OSCD OST LOCK OSCD OST LOCK T LOCK OSCD OST T OSCD = 102.4 μs for a OST © 2011 Microchip Technology Inc. ...
Page 83
... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T © 2011 Microchip Technology Inc. Vbor V BOR ...
Page 84
... DD ) for proper device operation. The BOR cir- crosses V DD has elapsed. The delay BOR ) is programmed by PWRT Reset Timer Value Select Section 27.0 “Special Features” initiated each time V BOR PWRT trip point BOR © 2011 Microchip Technology Inc. BOR bits DD ...
Page 85
... Reset state. This Reset state will not re- initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. © 2011 Microchip Technology Inc BOR PWRT ...
Page 86
... PWRSAV #IDLE instruction POR, BOR POR Section 27.8 “Code Protection and for more information on Cleared by: POR, BOR POR, BOR POR, BOR POR POR, BOR PWRSAV instruction, CLRWDT instruction, POR, BOR POR, BOR POR, BOR — — © 2011 Microchip Technology Inc. ...
Page 87
... These are summarized in Table 7-1. © 2011 Microchip Technology Inc. 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in and ...
Page 88
... Table 7-1 for the list of implemented interrupt vectors. DS70292E-page 88 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 (1) (1) © 2011 Microchip Technology Inc. ...
Page 89
... Microchip Technology Inc. AIVT Address 0x000104 Reserved 0x000106 Oscillator Failure 0x000108 Address Error 0x00010A Stack Error 0x00010C Math Error 0x00010E DMA Error 0x000110 Reserved 0x000112 Reserved 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – ...
Page 90
... C1TX – ECAN1 TX Data Request 0x0001A2 Reserved 0x0001A4 Reserved 0x0001A6 Reserved 0x0001A8 Reserved 0x0001AA Reserved 0x0001AC Reserved 0x0001AE Reserved 0x0001B0 DAC1R – DAC1 Right Data Request 0x0001B2 DAC1L – DAC1 Left Data Request 0x0001B4-0x0001FE Reserved Interrupt Source © 2011 Microchip Technology Inc. ...
Page 91
... IEC X The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2011 Microchip Technology Inc. 7.3.4 IPC X The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
Page 92
... R/W-0 R/W-0 R-0 US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Register 3- R/W bit 8 R/W-0 R/W bit 0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2011 Microchip Technology Inc. ...
Page 93
... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
Page 94
... STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70292E-page 94 © 2011 Microchip Technology Inc. ...
Page 95
... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...
Page 96
... Interrupt request has not occurred DS70292E-page 96 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA0IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 97
... Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70292E-page 97 ...
Page 98
... Interrupt request has not occurred DS70292E-page 98 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF CMIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC3IF DMA2IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 99
... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2011 Microchip Technology Inc. DS70292E-page 99 ...
Page 100
... DS70292E-page 100 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) (1) DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) U-0 U-0 — — bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 101
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 DCIEIF: DCI Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 R/W-0 U-0 DCIIF DCIEIF — U-0 ...
Page 102
... DS70292E-page 102 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 DMA6IF CRCIF U2EIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) (1) U-0 U-0 — — bit 8 R/W-0 U-0 U1EIF — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 103
... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 ...
Page 104
... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70292E-page 104 © 2011 Microchip Technology Inc. ...
Page 105
... INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 ...
Page 106
... Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70292E-page 106 © 2011 Microchip Technology Inc. ...
Page 107
... Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: Interrupts are disabled on devices without ECAN™ modules. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 108
... Unimplemented: Read as ‘0’ DS70292E-page 108 R/W-0 R/W-0 U-0 DCIIE DCIEIE — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 109
... Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN™ modules. 2: Interrupts are disabled on devices without Audio DAC modules. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — R/W-0 ...
Page 110
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292E-page 110 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 111
... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 112
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292E-page 112 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 113
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...
Page 114
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292E-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CMIP<2:0> bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 115
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
Page 116
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292E-page 116 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 117
... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 118
... Interrupts are disabled on devices without ECAN™ modules. DS70292E-page 118 R/W-0 U-0 R/W-1 (1) — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown (1) © 2011 Microchip Technology Inc. ...
Page 119
... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
Page 120
... Unimplemented: Read as ‘0’ DS70292E-page 120 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 DMA4IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 121
... DCIEIP<2:0>: DCI Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 U-0 U-0 — — U-0 U-0 U-0 — ...
Page 122
... Interrupt is priority 1 000 = Interrupt source is disabled DS70292E-page 122 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 RTCIP<2:0> bit 8 R/W-0 R/W-0 DCIIP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 123
... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
Page 124
... Interrupts are disabled on devices without ECAN™ modules. DS70292E-page 124 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 (1) C1TXIP<2:0> bit 8 R/W-0 R/W-0 DMA6IP<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 125
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without Audio DAC modules. © 2011 Microchip Technology Inc. R/W-0 U-0 R/W-0 (1) — U-0 U-0 U-0 — ...
Page 126
... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70292E-page 126 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2011 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 127
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2011 Microchip Technology Inc. 7.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, ...
Page 128
... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 128 © 2011 Microchip Technology Inc. ...
Page 129
... ECAN1 – TX Data Request DCI – Codec Transfer Done DAC1 – Right Data Output DAC2 – Left Data Output © 2011 Microchip Technology Inc. Direct Memory Access (DMA very efficient mechanism of copying data between peripheral SFRs (e.g., UART Receive register, Input Capture 1 buffer), ...
Page 130
... Alternatively, an interrupt can be generated when half of the block has been filled. Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2011 Microchip Technology Inc. ...
Page 131
... DMACS1, are common to all DMAC channels. DMACS0 contains the DMA RAM and SFR write colli- sion flags, XWCOLx and PWCOLx, respectively. DMACS1 indicates DMA channel and Ping-Pong mode status. © 2011 Microchip Technology Inc. The DMAxCON, DMAxREQ, DMAxPAD DMAxCNT are all conventional read/write registers. ...
Page 132
... Continuous, Ping-Pong modes disabled DS70292E-page 132 R/W-0 R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 R/W-0 — MODE<1:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 133
... The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources. © 2011 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 134
... Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 135
... CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> R/W-0 R/W-0 R/W-0 PAD< ...
Page 136
... No write collision detected DS70292E-page 136 R/C-0 R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 137
... Write collision detected write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2011 Microchip Technology Inc. DS70292E-page 137 ...
Page 138
... DMA0STB register selected 0 = DMA0STA register selected DS70292E-page 138 U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 139
... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2011 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...
Page 140
... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 140 © 2011 Microchip Technology Inc. ...
Page 141
... F are used interchangeably, except in the case of Doze mode Doze mode is used in any ratio other than 1:1, which is the default. © 2011 Microchip Technology Inc. • External and internal oscillator options as clock sources the • An on-chip Phase-Locked Loop (PLL) to scale the ...
Page 142
... External Clock (EC): External clock signal MHz. The external clock signal is directly applied to SOSCI pin. Section 27.1 “Configuration Configuration bits, FNOSC<2:0> bits, POSCMD<1:0> Table 9-1. is divided OSC ) and defines the given by: DEVICE OPERATING FREQUENCY F OSC F = ------------- CY 2 © 2011 Microchip Technology Inc. ...
Page 143
... X04 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2011 Microchip Technology Inc. For a primary oscillator or FRC oscillator, output ‘F the PLL output ‘F EQUATION 9-2: For example, suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL. • ...
Page 144
... DS70292E-page 144 Oscillator Source POSCMD<1:0> Internal xx Internal xx Internal xx Secondary xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx See FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 — 011 — 011 1 011 — 010 — 010 1 010 1 001 1 000 © 2011 Microchip Technology Inc. ...
Page 145
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (1,3) R-0 U-0 R/W-y — ...
Page 146
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 3: This register is reset only on a Power-on Reset (POR). DS70292E-page 146 (1,3) (CONTINUED) © 2011 Microchip Technology Inc. ...
Page 147
... Input/33 • • • 00000 = Input/2 (default) 00001 = Input/3 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. 2: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (2) R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...
Page 148
... This register is reset only on a Power-on Reset (POR). DS70292E-page 148 (1) U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 149
... OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. 2: This register is reset only on a Power-on Reset (POR). © 2011 Microchip Technology Inc. (2) U-0 U-0 U-0 — ...
Page 150
... This register is reset only on a Power-on Reset (POR). DS70292E-page 150 (1) R/W-0 R/W-0 R/W-0 AOSCMD<1:0> U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 APSTSCLR<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 151
... NOSC control bits. If they are the same, the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. © 2011 Microchip Technology Inc valid clock switch has been initiated, the status bits, LOCK (OSCCON<5>) and the CF (OSCCON< ...
Page 152
... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 152 © 2011 Microchip Technology Inc. ...
Page 153
... Configuration”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2011 Microchip Technology Inc. 10.2 Instruction-Based Power-Saving Modes dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices have two and special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 154
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). There are eight possible ® DSC © 2011 Microchip Technology Inc. ...
Page 155
... Unimplemented: Read as ‘0’ bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled © 2011 Microchip Technology Inc. R/W-0 R/W-0 U-0 T2MD T1MD — R/W-0 R/W-0 ...
Page 156
... Output Compare 1 module is enabled DS70292E-page 156 U-0 U-0 U-0 — — — U-0 R/W-0 R/W-0 — OC4MD OC3MD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 IC2MD IC1MD bit 8 R/W-0 R/W-0 OC2MD OC1MD bit Bit is unknown © 2011 Microchip Technology Inc. ...
Page 157
... CRCMD: CRC Module Disable bit 1 = CRC module is disabled 0 = CRC module is enabled bit 6 DAC1MD: DAC1 Module Disable bit 1 = DAC1 module is disabled 0 = DAC1 module is enabled bit 5-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. U-0 U-0 R/W-0 — — CMPMD U-0 U-0 U-0 — ...
Page 158
... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 158 © 2011 Microchip Technology Inc. ...
Page 159
... WR Port Data Latch Read LAT Read Port © 2011 Microchip Technology Inc. has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through,” in which a port’s digital output can drive the input of a peripheral that shares the same pin. ...
Page 160
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Example 11-1. dsPIC33FJ32GP302/304, © 2011 Microchip Technology Inc. ...
Page 161
... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2011 Microchip Technology Inc. 11.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it is mapped to ...
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... RPINR23 CSDI RPINR24 CSCK RPINR24 COFS RPINR25 CIRX RPINR26 (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> T4CKR<4:0> T5CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> U2RXR<4:0> U2CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0> CSDIR<4:0> CSCKR<4:0> COFSR<4:0> CIRXR<4:0> © 2011 Microchip Technology Inc. ...
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... SCK2 SS2 CSDO CSCK COFS C1TX OC1 OC2 OC3 OC4 © 2011 Microchip Technology Inc. FIGURE 11-3: U1TX Output enable U1RTS Output enable 4 11-29). The U1RTS Output 4 RPn tied to default port pin 00000 RPn tied to Comparator1 Output 00001 RPn tied to Comparator2 Output ...
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... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. © 2011 Microchip Technology Inc. ...
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... INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ © 2011 Microchip Technology Inc. IOLOCK bit to ‘0’. See Register R/W-1 R/W-1 INT1R<4:0> ...
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... Input tied to RP1 00000 = Input tied to RP0 DS70292E-page 166 U-0 U-0 — — R/W-1 R/W-1 INT2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ...
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... Input tied to RP1 00000 = Input tied to RP0 DS70292E-page 168 R/W-1 R/W-1 T5CKR<4:0> R/W-1 R/W-1 T4CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25. • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ...
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... Input tied to RP1 00000 = Input tied to RP0 DS70292E-page 170 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... OCFAR<4:0>: Assign Output Compare A (OCFA) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as ‘0’ ...
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... Input tied to RP1 00000 = Input tied to RP0 DS70292E-page 172 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... U2RXR<4:0>: Assign UART2 Receive (U2RX) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. R/W-1 R/W-1 U2CTSR<4:0> R/W-1 R/W-1 U2RXR<4:0> Unimplemented bit, read as ‘0’ ...
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... Input tied to RP1 00000 = Input tied to RP0 DS70292E-page 174 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... SS1R<4:0>: Assign SPI1 Slave Select Input (SS1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 SS1R<4:0> ...
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... Input tied to RP1 00000 = Input tied to RP0 DS70292E-page 176 R/W-1 R/W-1 SCK2R<4:0> R/W-1 R/W-1 SDI2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... SS2R<4:0>: Assign SPI2 Slave Select Input (SS2) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 SS2R<4:0> ...
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... Input tied to RP1 00000 = Input tied to RP0 DS70292E-page 178 R/W-1 R/W-1 CSCKR<4:0> R/W-1 R/W-1 CSDIR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 Note 1: This register is disabled on devices without an ECAN™ module. © 2011 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 COFSR<4:0> Unimplemented bit, read as ‘0’ ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...
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... RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R< ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...
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... RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see peripheral function numbers) © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R< ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 4-0 RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2011 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP21R<4:0> R/W-0 R/W-0 R/W-0 RP20R< ...
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... This register is implemented in 44-pin devices only. DS70292E-page 186 R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 R/W-0 R/W-0 RP24R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown Table 11-2 for Table 11-2 for © 2011 Microchip Technology Inc. ...
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... TCKPS<1:0> SOSCI (1) LPOSCEN Note 1: Refer to Section 9.0 “Oscillator Configuration” © 2011 Microchip Technology Inc. The unique features of Timer1 allow used for Real-Time Clock (RTC) applications. A block diagram of Timer1 is shown in The Timer1 module can operate in one of the following and modes: • ...
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... Unimplemented: Read as ‘0’ DS70292E-page 188 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... CY TCKPS<1:0> Prescaler Sync TxCK TCKPS<1:0> © 2011 Microchip Technology Inc. • A Type B timer can be concatenated with a Type C timer to form a 32-bit timer • The external clock input (TxCK) is always synchronized to the internal device clock and the clock synchronization is performed after the prescaler. ...
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... The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. Table 13-2. 32-BIT TIMER TYPE C Timer (msw) Timer3 Timer5 Figure 13-3. The 32-bit timer module © 2011 Microchip Technology Inc. ...
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... F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers 2: Timer Type B Timer ( and 4) 3: Timer Type C Timer ( and 5) © 2011 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw TMRx TMRy 00 x1 TMRyHLD ...
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... Unimplemented: Read as ‘0’ DS70292E-page 192 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit must be cleared to operate the 32-bit timer in Idle mode. 2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), these bits have no effect. © 2011 Microchip Technology Inc. U-0 U-0 (1) — ...
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... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 194 © 2011 Microchip Technology Inc. ...
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... Edge Detection Mode Sleep/Idle Wake-up Mode Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2011 Microchip Technology Inc. 1. Simple Capture Event modes: - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of ...
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... Input capture module turned off DS70292E-page 196 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2011 Microchip Technology Inc. ...
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... TMR3 TMR2 © 2011 Microchip Technology Inc. The Output Compare module can select either Timer2 or Timer3 for its time base. The module compares the value of the timer with the value of one or two compare registers depending on the operating mode selected. and The state of the output pin changes when the timer value matches the compare register value ...
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... OCx Falling edge 1 Current output is maintained OCx Rising and Falling edge OCx Falling edge 0 OCx Falling edge OCxR is zero No interrupt 1, if OCxR is non-zero OCFA Falling edge for OC1 to OC4 1, if OCxR is non-zero Timer is reset on period match — © 2011 Microchip Technology Inc. ...
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... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2011 Microchip Technology Inc. U-0 U-0 U-0 — ...
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... AND dsPIC33FJ128GPX02/X04 NOTES: DS70292E-page 200 © 2011 Microchip Technology Inc. ...