DSPIC33FJ128GP206A-I/MR Microchip Technology, DSPIC33FJ128GP206A-I/MR Datasheet - Page 66

• Manufacturer Part Number: DSPIC33FJ128GP206A-I/MR
• Description: IC DSPIC MCU/DSP 128K 64-QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP206A-I/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 18x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Product: DSCs
• Processor Series: DSPIC33F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-24:
TABLE 4-25:
TABLE 4-26:
TRISA
PORTA
LATA
ODCA
Legend:
Note
TRISB
PORTB
LATB
Legend:
Note
DCICON1
DCICON2
DCICON3
DCISTAT
TSCON
RSCON
RXBUF0
RXBUF1
RXBUF2
RXBUF3
TXBUF0
TXBUF1
TXBUF2
TXBUF3
Legend:
Note
File Name
File Name
Name
SFR
(2)
1:
1:
1:
Addr.
0280
0282
0284
0286
0288
028C
0290
0292
0294
0296
0298
029A
029C
029E
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
— = unimplemented, read as ‘0’.
Refer to the “dsPIC33F/PIC24H Family Reference Manual” for descriptions of register bit fields.
Addr
02C0
02C2
02C4
06C0
Addr
02C6
02C8
02CA
DCIEN
RSE15
TSE15
DCI REGISTER MAP
Bit 15
PORTA REGISTER MAP
PORTB REGISTER MAP
TRISA15
ODCA15
TRISB15
LATA15
LATB15
Bit 15
—
—
—
Bit 15
RA15
RB15
TSE14
RSE14
Bit 14
—
—
—
—
TRISA14
ODCA14
TRISB14
LATA14
LATB14
Bit 14
Bit 14
RA14
RB14
DCISIDL
TSE13
RSE13
Bit 13
TRISA13
—
—
—
TRISB13
LATA13
LATB13
Bit 13
Bit 13
RA13
RB13
—
RSE12
TSE12
Bit 12
TRISA12
TRISB12
—
—
—
—
LATA12
LATB12
Bit 12
Bit 12
RA12
(1)
RB12
(1)
—
DLOOP
BLEN1
SLOT3
RSE11
TSE11
Bit 11
TRISB11
Bit 11
LATB11
Bit 11
RB11
—
—
—
—
CSCKD
BLEN0
SLOT2
TSE10
RSE10
Bit 10
TRISA10
TRISB10
LATA10
LATB10
Bit 10
Bit 10
RA10
RB10
—
Transmit Buffer #0 Data Register
Transmit Buffer #1 Data Register
Transmit Buffer #2 Data Register
Transmit Buffer #3 Data Register
Receive Buffer #0 Data Register
Receive Buffer #1 Data Register
Receive Buffer #2 Data Register
Receive Buffer #3 Data Register
CSCKE
SLOT1
TSE9
RSE9
Bit 9
—
TRISB9
LATB9
TRISA9
Bit 9
LATA9
RB9
Bit 9
RA9
—
COFSD
SLOT0
TSE8
RSE8
Bit 8
TRISB8
LATB8
Bit 8
RB8
Bit 8
—
—
—
—
UNFM
RSE7
COFSG<3:0>
TSE7
Bit 7
—
TRISB7
LATB7
TRISA7
LATA7
Bit 7
Bit 7
RB7
RA7
CSDOM
—
BCG<11:0>
TSE6
RSE6
Bit 6
—
TRISA6
TRISB6
LATA6
Bit 6
LATB6
RA6
Bit 6
RB6
RSE5 RSE4 RSE3
—
DJST
TSE5
Bit 5
—
TSE4
Bit 4
TRISA5
ODCA5
TRISB5
LATA5
LATB5
Bit 5
—
—
—
Bit 5
RA5
RB5
TSE3
Bit 3
ROV
—
TRISB4
LATB4
TRISA4
ODCA4
Bit 4
LATA4
RB4
Bit 4
RA4
RFUL
RSE2
TSE2
Bit 2
—
TRISB3
WS<3:0>
LATB3
Bit 3
TRISA3
ODCA3
RB3
LATA3
Bit 3
COFSM1
RA3
TUNF
TSE1
RSE1
Bit 1
TRISB2
LATB2
TRISA2
ODCA2
Bit 2
RB2
LATA2
Bit 2
RA2
COFSM0 0000 0000 0000 0000
TMPTY
RSE0
TSE0
Bit 0
TRISB1
LATB1
Bit 1
TRISA1
ODCA1
RB1
LATA1
Bit 1
RA1
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TRISB0
LATB0
Reset State
Bit 0
RB0
TRISA0
ODCA0
LATA0
Bit 0
RA0
Resets
Resets
FFFF
xxxx
xxxx
F6FF
xxxx
xxxx
0000
All
All