DSPIC30F4012-30I/SO Microchip Technology, DSPIC30F4012-30I/SO Datasheet
DSPIC30F4012-30I/SO
Specifications of DSPIC30F4012-30I/SO
Available stocks
Related parts for DSPIC30F4012-30I/SO
DSPIC30F4012-30I/SO Summary of contents
Page 1
... Microchip Technology Inc. dsPIC30F4011/4012 High-Performance, 16-Bit Digital Signal Controllers Data Sheet DS70135G ...
Page 2
... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... All DSP instructions are single cycle • ±16-bit, single-cycle shift © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Timer module with programmable prescaler: - Five 16-bit timers/counters; optionally pair 16-bit timers into 32-bit timer modules • ...
Page 4
... Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes dsPIC30F Motor Control and Power Conversion Family Program SRAM Device Pins Mem. Bytes/ Bytes Instructions dsPIC30F4012 28 48K/16K 2048 dsPIC30F4011 40/44 48K/16K 2048 DS70135G-page 4 CMOS Technology: • Low-power, high-speed Flash technology • ...
Page 5
... Pin Diagrams 40-Pin PDIP EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 OSC2/CLKO/RC15 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 EMUD2/OC2/IC2/INT2/RD1 44-Pin TQFP PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 C1TX/RF1 C1RX/RF0 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 MCLR +/CN2/RB0 REF -/CN3/RB1 PWM1L/RE0 REF 4 37 PWM1H/RE1 5 36 PWM2L/RE2 6 35 ...
Page 6
... QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 C1TX/RF1 C1RX/RF0 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V DS70135G-page dsPIC30F4011 OSC2/CLKO/RC15 OSC1/CLKI AN8/RB8 AN7/RB7 AN6/OCFA/RB6 AN5/QEB/IC8/CN7/RB5 AN4/QEA/IC7/CN6/RB4 externally. SS © 2010 Microchip Technology Inc. ...
Page 7
... The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © 2010 Microchip Technology Inc. dsPIC30F4011/4012 MCLR +/CN2/RB0 -/CN3/RB1 PWM1L/RE0 3 26 PWM1H/RE1 4 25 PWM2L/RE2 5 24 PWM2H/RE3 6 23 PWM3L/RE4 PWM3H/RE5 SS OSC1/CLKI PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2 11 18 PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3 FLTA/INT0/SCK1/OCFA/RE8 EMUC2/OC1/IC1/INT1/RD0 dsPIC30F4012 OSC2/CLKO/RC15 32 OSC1/CLKI AN5/QEB/IC8/CN7/RB5 23 AN4/QEA/IC7/CN6/RB4 externally. SS DS70135G-page 7 ...
Page 8
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS70135G-page 8 to receive the most current information on all of our products. © 2010 Microchip Technology Inc. ...
Page 9
... The dsPIC30F devices contain extensive Digital Signal Processor (DSP) functionality within a high-performance, 16-bit microcontroller (MCU) architecture. Figure 1-2 illustrate device block diagrams for the dsPIC30F4011 and dsPIC30F4012 devices. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Manual” Figure 1-1 and ...
Page 10
... PORTE PORTF EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/CN4/RB2 AN3/INDX/CN5/RB3 AN4/QEA/IC7/CN6/RB4 AN5/QEB/IC8/CN7/RB5 AN6/OCFA/RB6 AN7/RB7 AN8/RB8 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 EMUD2/OC2/IC2/INT2/RD1 OC3/RD2 OC4/RD3 PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 FLTA/INT0/RE8 C1RX/RF0 C1TX/RF1 PGC/EMUC/U1RX/SDI1/SDA/RF2 PGD/EMUD/U1TX/SDO1/SCL/RF3 U2RX/CN17/RF4 U2TX/CN18/RF5 SCK1/RF6 © 2010 Microchip Technology Inc. ...
Page 11
... FIGURE 1-2: dsPIC30F4012 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH PCL Program Counter Stack Loop Address Latch Control Control Logic Logic Program Memory (48 Kbytes) Data EEPROM (1 Kbyte) 16 Data Latch ROM Latch ...
Page 12
... PWM2 high output. PWM3 low output. PWM3 high output. Master Clear (Reset) input or programming voltage input. This pin is an active-low Reset to the device. Compare Fault A input (for Compare channels and 4). Compare outputs 1 through 4. Analog = Analog input Output Power © 2010 Microchip Technology Inc. ...
Page 13
... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Description Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ...
Page 14
... Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. TABLE 1-2: dsPIC30F4012 I/O PIN DESCRIPTIONS Pin Buffer Pin Name Type Type ...
Page 15
... TABLE 1-2: dsPIC30F4012 I/O PIN DESCRIPTIONS (CONTINUED) Pin Buffer Pin Name Type Type OSC1 I ST/CMOS OSC2 I/O — PGD I/O ST PGC I ST RB0-RB5 I/O ST RC13-RC15 I/O ST RD0-RD1 I/O ST RE0-RE5, I/O ST RE8 RF2-RF3 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SS1 I/O ...
Page 16
... NOTES: DS70135G-page 16 © 2010 Microchip Technology Inc. ...
Page 17
... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 • SWWLinear indirect access of 32K word pages within program space is also possible, using any working register via table read and write instruc- tions ...
Page 18
... Adder/Subtracter Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear; therefore, the PC can address instruction words. Figure 2-1 for SR layout. © 2010 Microchip Technology Inc. ...
Page 19
... DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG 22 DOSTART OAB SAB DA SRH © 2010 Microchip Technology Inc. dsPIC30F4011/4012 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 ...
Page 20
... Unsigned divide: Wm/Wn → W0; Rem → block diagram of the DSP engine is shown in Figure 2-2. TABLE 2-2: Instruction CLR ED EDAC MAC MOVSAC MPY MPY.N MSC selection Table 3-3. DSP INSTRUCTION SUMMARY Algebraic Operation – – change – – © 2010 Microchip Technology Inc. ...
Page 21
... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In © 2010 Microchip Technology Inc. dsPIC30F4011/4012 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill DS70135G-page 21 ...
Page 22
... Overflow Trap Flag Enable bit (OVATE, OVBTE) in the INTCON1 register (refer to “Interrupts”) is set. This allows the user to take immediate action, for example, to correct system gain. trap when set and the Section 5.0 © 2010 Microchip Technology Inc. ...
Page 23
... No saturation operation is performed and the accumulator is allowed to overflow (destroying its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 2.4.2.2 Accumulator ‘Write-Back’ The MAC class of instructions (with the exception of MPY, MPY ...
Page 24
... The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions for right shifts, and bit positions for left shifts. © 2010 Microchip Technology Inc. ...
Page 25
... TBLPAG<7> to determine user or configura- tion space access. In Table 3-1, read/write instructions, bit 23 allows access to the Device ID, the User ID and the Configuration bits; otherwise, bit 23 is always clear. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F4011/4012 Reset – ...
Page 26
... Note: Program Space Visibility cannot be used to access bits <23:16> word in program memory. DS70135G-page 26 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA <15> <14:1> <0> PC<22:1> 0 Data EA<15:0> Data EA<15:0> Data EA<14:0> 0 Byte Select © 2010 Microchip Technology Inc. ...
Page 27
... Program Memory ‘Phantom’ Byte (read as ‘0’). © 2010 Microchip Technology Inc. dsPIC30F4011/4012 A set of table instructions is provided to move byte or word-sized data to and from program space (see Figure 3-3 and Figure 1. TBLRDL: Table Read Low Word: Read the lsw of the program address ...
Page 28
... Execution in the last iteration - Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop allows the instruction, accessing data using PSV, to execute in a single cycle 3-5. © 2010 Microchip Technology Inc. ...
Page 29
... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Program Space 0x0000 (1) PSVPAG ...
Page 30
... Optionally Mapped into Program Memory 0xFFFF DS70135G-page 30 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x8000 X Data Unimplemented (X) 0xFFFE LSB 4096 Bytes Near Data Space © 2010 Microchip Technology Inc. ...
Page 31
... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2010 Microchip Technology Inc. dsPIC30F4011/4012 SFR SPACE UNUSED Y SPACE UNUSED UNUSED MAC Class Ops Read-Only ...
Page 32
... Fault. FIGURE 3-8: 15 0001 Byte 1 0x0000 Byte 3 0003 0x0000 Byte 5 0005 0x0000 ® DATA ALIGNMENT MSB LSB 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2010 Microchip Technology Inc. ...
Page 33
... Note push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> ...
Page 34
TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 ...
Page 35
TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend uninitialized bit; — = unimplemented ...
Page 36
... NOTES: DS70135G-page 36 © 2010 Microchip Technology Inc. ...
Page 37
... Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2010 Microchip Technology Inc. dsPIC30F4011/4012 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
Page 38
... The only exception to the usage restrictions is for buf- fers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). © 2010 Microchip Technology Inc. ...
Page 39
... MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2010 Microchip Technology Inc. dsPIC30F4011/4012 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- ister, MODCON<15:0>, contains enable flags as well 3-3). ...
Page 40
... W register that has been designated as the Bit-Reversed Pointer. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer N bytes, should not be enabled to do this, Bit-Reversed Modulo Addressing will © 2010 Microchip Technology Inc. ...
Page 41
... BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 32768 16384 8192 4096 2048 1024 512 256 128 Note 1: Modifier values for buffer sizes greater than 1024 words will exceed the available data memory on the dsPIC30F4011/4012 devices. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Bit-Reversed Address Decimal ...
Page 42
... NOTES: DS70135G-page 42 © 2010 Microchip Technology Inc. ...
Page 43
... The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers ...
Page 44
... Reserved 36 44 Reserved 37 45 Reserved 38 46 Reserved 39 47 PWM – PWM Period Match 40 48 QEI – QEI Interrupt 41 49 Reserved 42 50 Reserved 43 51 FLTA – PWM Fault Reserved 45-53 53-61 Reserved Lowest Natural Order Priority © 2010 Microchip Technology Inc. ...
Page 45
... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 5.3 Traps Traps can be considered as non-maskable interrupts, indicating a software or hardware error which adhere to ...
Page 46
... Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector — — — Interrupt 52 Vector Interrupt 53 Vector © 2010 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 0x00007E 0x000080 0x000082 0x000084 0x000094 0x0000FE ...
Page 47
... The RETFIE (return from interrupt) instruction will unstack the program counter and STATUS registers to return the processor to its state prior to the interrupt sequence. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 5.5 Alternate Interrupt Vector Table In program memory, the Interrupt Vector Table (IVT) is ...
Page 48
TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF ...
Page 49
... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2010 Microchip Technology Inc. dsPIC30F4011/4012 6.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time, and can write program memory data, 32 instructions (96 bytes time ...
Page 50
... NVMKEY register. Refer to “Programming Operations” Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. © 2010 Microchip Technology Inc. Section 6.6 for further details. ...
Page 51
... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2010 Microchip Technology Inc. dsPIC30F4011/4012 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Set up NVMCON register for multi-word, program Flash, program and set WREN bit. ...
Page 52
... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority < for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted © 2010 Microchip Technology Inc. ...
Page 53
TABLE 6-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — ...
Page 54
... NOTES: DS70135G-page 54 © 2010 Microchip Technology Inc. ...
Page 55
... A word write operation should be preceded by an erase of the corresponding memory location(s). The write typically requires complete, but the write time will vary with voltage and temperature. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 A program or erase operation on the data EEPROM does not stop the instruction flow. The user is respon- ...
Page 56
... Block all interrupts with priority < for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 ; for next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence © 2010 Microchip Technology Inc. ...
Page 57
... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
Page 58
... The NVMADR captures last table access address. ; Select data EEPROM for multi word op ; Operate Key to allow program operation ; Block all interrupts with priority < for next 5 instructions ; Write the 0x55 key ; Write the 0xAA key ; Start write cycle © 2010 Microchip Technology Inc. ...
Page 59
... This should be used in applications where excessive writes can stress bits near the specification limit. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 7.5 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
Page 60
... NOTES: DS70135G-page 60 © 2010 Microchip Technology Inc. ...
Page 61
... WR TRIS WR LAT + WR PORT Read LAT Read PORT © 2010 Microchip Technology Inc. dsPIC30F4011/4012 the latch. Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins and writes to the port pins, write the latch (LATx). Any bit and its associated data and control registers that are not valid for a particular device will be disabled ...
Page 62
... Typically this instruction would be a NOP will be OL EXAMPLE 8-1: MOV 0xFF00 Configure PORTB<15:8> MOV W0, TRISBB ; and PORTB<7:0> as outputs NOP BTSS PORTB, #13 ; Next Instruction I/O Cell I/O Pad Input Data PORT WRITE/READ EXAMPLE ; as inputs ; Delay 1 cycle © 2010 Microchip Technology Inc. ...
Page 63
TABLE 8-1: dsPIC30F4011 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CA — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 ...
Page 64
... TABLE 8-2: dsPIC30F4012 PORT REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISB 02C6 — — — — PORTB 02C8 — — — — LATB 02CB — — — — TRISC 02CC TRISC15 TRISC14 TRISC13 — PORTC 02CE RC15 RC14 RC13 — ...
Page 65
... Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: These bits are not available on dsPIC30F4012 devices. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 66
... NOTES: DS70135G-page 66 © 2010 Microchip Technology Inc. ...
Page 67
... Timer operation during CPU Idle and Sleep modes • Interrupt on 16-bit Period register match or falling edge of external gate signal © 2010 Microchip Technology Inc. dsPIC30F4011/4012 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. presents a block diagram of the 16-bit timer module. ...
Page 68
... Period register and be reset to 0x0000. When a match between the timer and the Period regis- ter occurs, an interrupt can be generated if the respective timer interrupt enable bit is asserted. TSYNC Sync 1 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2010 Microchip Technology Inc. ...
Page 69
... XTAL SOSCO pF 100K © 2010 Microchip Technology Inc. dsPIC30F4011/4012 9.5.1 RTC OSCILLATOR OPERATION When TON = 1, TCS = 1 and TGATE = 0, the timer increments on the rising edge of the 32 kHz LP oscilla- tor output signal the value specified in the Period register, and is then reset to ‘0’. ...
Page 70
TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note ...
Page 71
... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer ...
Page 72
... Timer configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70135G-page 72 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 x Gate 0 1 Sync TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2010 Microchip Technology Inc. ...
Page 73
... T3IF Event Flag 1 TGATE Note: The dsPIC30F4011/4012 devices do not have external pin inputs to Timer3. In these devices, the following modes should not be used: 1. TCS = 1. 2. TCS = 0 and TGATE = 1 (gated time accumulation). © 2010 Microchip Technology Inc. dsPIC30F4011/4012 PR2 TMR2 Q D TGATE Q CK ...
Page 74
... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective Timer Interrupt Enable bit, T3IE (IEC0<7>). © 2010 Microchip Technology Inc. ...
Page 75
TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
Page 76
... NOTES: DS70135G-page 76 © 2010 Microchip Technology Inc. ...
Page 77
... T4CK is not implemented and this line is tied Timer configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The Timer4/5 module is similar in operation to the Timer 2/3 module. However, there are some differences, which are as follows: • ...
Page 78
... TCS = 1. 2. TCS = 0 and TGATE = 1 (gated time accumulation). DS70135G-page 78 PR4 TMR4 Q D TGATE Gate Sync PR5 Comparator x 16 TMR5 Q D TGATE Q CK Sync Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2010 Microchip Technology Inc. ...
Page 79
TABLE 11-1: TIMER4/5 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON — TSIDL — T5CON 0120 TON — TSIDL — Legend: u ...
Page 80
... NOTES: DS70135G-page 80 © 2010 Microchip Technology Inc. ...
Page 81
... ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The key operational features of the input capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...
Page 82
... Moreover, the ICSIDL bit must be asserted to a logic ‘0’. If the input capture module is ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin. © 2010 Microchip Technology Inc. defined as ...
Page 83
... Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx register. Enabling an interrupt is accomplished via the respec- tive Capture Channel Interrupt Enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IECx register. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 DS70135G-page 83 ...
Page 84
TABLE 12-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — IC7BUF 0158 IC7CON 015A — — ICSIDL ...
Page 85
... TMR3<15:0> TMR2<15:0 Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through N. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
Page 86
... The OCFLT bit (OCxCON<4>) indicates whether a Fault condition has occurred. This state will be maintained until both of the following events have occurred: • The external Fault condition has been removed • The PWM mode has been re-enabled by writing to the appropriate control bits © 2010 Microchip Technology Inc ...
Page 87
... PWM period comparisons. Timer3 is referred to in the figure for clarity. FIGURE 13-1: PWM OUTPUT TIMING Duty Cycle TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS © 2010 Microchip Technology Inc. dsPIC30F4011/4012 • OSC Period TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS ...
Page 88
... IFS0 register and must be cleared in software. The interrupt is enabled via the respective Timer Interrupt Enable bit (T2IE or T3IE) located in the IEC0 register. The output compare interrupt flag is never set during the PWM mode of operation. © 2010 Microchip Technology Inc. ...
Page 89
... OCSIDL — Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: These registers are not available on dsPIC30F4012 devices. (1) Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Output Compare 1 Secondary Register Output Compare 1 Main Register — ...
Page 90
... NOTES: DS70135G-page 90 © 2010 Microchip Technology Inc. ...
Page 91
... INDX Digital Filter 3 Up/Down Note: In dsPIC30F4011/4012, the UPDN pin is not available. Up/Down logic bit can still be polled by software. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The operational features of the QEI include: • Three input channels for two phase signals and index pulse • ...
Page 92
... UPDN signal is supplied to an SFR bit, UPDN (QEICON<11>), as a read-only bit. Note: QEI pins are multiplexed with analog inputs. The user must insure that all QEI associated pins are set as digital inputs in the ADPCFG register. © 2010 Microchip Technology Inc. ...
Page 93
... CY To enable the filter output for channels QEA, QEB and INDX, the QEOUT bit must be ‘1’. The filter network for all channels is disabled on POR and BOR. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 14.5 Alternate 16-bit Timer/Counter When the QEI module is not configured for the QEI mode, QEIM< ...
Page 94
... The QEI Interrupt Flag bit, QEIIF, is asserted upon occurrence of any of the above events. The QEIIF bit must be cleared in software. QEIIF is located in the IFS2 register. Enabling an interrupt is accomplished via the respec- tive Enable bit, QEIIE. The QEIIE bit is located in the IEC2 register. © 2010 Microchip Technology Inc. ...
Page 95
TABLE 14-1: QEI REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name QEICON 0122 CNTERR — QEISIDL INDX UPDN DFLTCON 0124 — — — — POSCNT 0126 MAXCNT 0128 ADPCFG 02A8 — — ...
Page 96
... NOTES: DS70135G-page 96 © 2010 Microchip Technology Inc. ...
Page 97
... Three-Phase AC Induction Motor • Switched Reluctance (SR) Motor • Brushless DC (BLDC) Motor • Uninterruptible Power Supply (UPS) © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The PWM module has the following features: • 6 PWM I/O pins with 3 duty cycle generators • 16-bit resolution • ...
Page 98
... Generator and Override Logic PWM Channel 2 Dead-Time Generator 2 Generator and Override Logic PWM Channel 1 Dead-Time Generator 1 Generator and Override Logic Special Event Postscaler PTDIR PWM3H PWM3L PWM2H Output PWM2L Driver Block PWM1H PWM1L FLTA Special Event Trigger © 2010 Microchip Technology Inc. ...
Page 99
... Motors (ECMs). The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 15.1.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base counts upwards until the value in the Time Base Period regis- ter (PTPER) is matched ...
Page 100
... PWM frequency can be determined using Equation 15-3: EQUATION 15-3: Resolution = can be determined using PWM PERIOD • (PTPER + 1) PTMR Prescale Value 15-2. PWM PERIOD (CENTER-ALIGNED MODE) • • 2 PTPER + 1) PTMR Prescale Value PWM RESOLUTION • log ( PWM CY log (2) © 2010 Microchip Technology Inc. ...
Page 101
... New Duty Cycle Latched PTPER PTMR Value 0 Duty Cycle Period © 2010 Microchip Technology Inc. dsPIC30F4011/4012 15.4 Center-Aligned PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in a Continuous Up/Down Count mode (see The PWM compare output is driven to the active state ...
Page 102
... The two dead times can be assigned to individual PWM I/O pin pairs. This operating mode allows the PWM module to drive different transistor/load combinations with each complementary PWM I/O pin pair. © 2010 Microchip Technology Inc. ...
Page 103
... FIGURE 15-4: DEAD-TIME TIMING DIAGRAM Duty Cycle Generator PWMxH PWMxL Dead-Time A (Active) © 2010 Microchip Technology Inc. dsPIC30F4011/4012 DTAPS<1:0> control bits in the DTCON1 SFR. One of four clock prescaler options (T may be selected. After the prescaler value is selected, the dead time is 15-4, each adjusted by loading 6-bit unsigned values into the DTCON1 SFR ...
Page 104
... OVDCON register are synchronized to the PWM time base. Synchronous output overrides occur at the following times: • Edge-Aligned mode when PTMR is zero. • Center-Aligned modes when PTMR is zero and when the value of PTMR matches PTPER. © 2010 Microchip Technology Inc. six bits, ...
Page 105
... Fault pin could be used as a general purpose interrupt pin. The Fault pin has an interrupt vector, interrupt flag bit and interrupt priority bits associated with it. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 15.12.2 FAULT STATES The FLTACON Special Function Register has six bits that determine the state of each PWM I/O pin when it is overridden by a Fault input ...
Page 106
... The PTCON SFR contains a PTSIDL control bit. This bit determines if the PWM module will continue to operate or stop when the device enters Idle mode. If PTSIDL = 0, the module will continue to operate. If PTSIDL = 1, the module will stop operation as long as the CPU remains in Idle mode. © 2010 Microchip Technology Inc. ...
Page 107
TABLE 15-1: 6-OUTPUT PWM REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 PTCON 01C0 PTEN — PTSIDL — PTMR 01C2 PTDIR PTPER 01C4 — SEVTCMP 01C6 SEVTDIR PWMCON1 01C8 — — — — PWMCON2 01CA ...
Page 108
... NOTES: DS70135G-page 108 © 2010 Microchip Technology Inc. ...
Page 109
... The module will not respond to SCL transitions while SPIROV is ‘1’, effectively disabling the module until SPI1BUF is read by user software. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Transmit writes are also double-buffered. The user writes to SPI1BUF. When the master or slave transfer is completed, the contents of the shift register (SPI1SR) is moved to the receive buffer ...
Page 110
... Shift Clock Clock Edge Control Select Secondary Prescaler Enable Master Clock SDO1 SDI1 Serial Input Buffer SDI1 SDO1 MSb Serial Clock SCK1 SCK1 Primary F CY Prescaler 1, 4, 16, 64 SPI Slave (SPI1BUF) Shift Register (SPI1SR) LSb PROCESSOR 2 © 2010 Microchip Technology Inc. ...
Page 111
... Therefore, when the SS1 pin is asserted low again, transmission/reception will begin at the MSb, even if SS1 had been deasserted in the middle of a transmit/receive. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 16.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shut down ...
Page 112
TABLE 16-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Legend uninitialized bit; ...
Page 113
... Thus, the I C module can operate either as a slave master bus. FIGURE 17-1: PROGRAMMER’S MODEL bit 15 bit 15 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 17.1.1 VARIOUS I The following types • slave operation with 7-bit addressing 2 • slave operation with 10-bit addressing 2 • ...
Page 114
... DS70135G-page 114 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Collision Detect Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2010 Microchip Technology Inc. ...
Page 115
... SCL high (see timing diagram). The inter- rupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 17.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 116
... C bus have deasserted SCL. This ensures that a write to the SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. © 2010 Microchip Technology Inc. ...
Page 117
... When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the I2CRCV to determine if the address was device-specific or a general call address. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 2 17. Master Support As a master device, six operations are supported. ...
Page 118
... For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. C master event Interrupt Service Routine 2 C bus is 2 © 2010 Microchip Technology Inc. C ...
Page 119
TABLE 17-2: I C™ REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN ...
Page 120
... NOTES: DS70135G-page 120 © 2010 Microchip Technology Inc. ...
Page 121
... FIGURE 18-1: UART TRANSMITTER BLOCK DIAGRAM Internal Data Bus UTXBRK Data UxTX Parity Note dsPIC30F4012 only has UART1. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 18.1 UART Module Overview The key features of the UART module are: • Full-Duplex 9-bit Data Communication • Even, Odd or No Parity Options (for 8-bit data) • ...
Page 122
... Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) ÷ 16 Divider 16x Baud Clock from Baud Rate Generator Read Read Write UxSTA Control Signals UxRXIF © 2010 Microchip Technology Inc. ...
Page 123
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2010 Microchip Technology Inc. dsPIC30F4011/4012 18.3 Transmitting Data 18.3.1 ...
Page 124
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. © 2010 Microchip Technology Inc. RXB) ...
Page 125
... FERR bit set. The Break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not been received yet. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 18.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 126
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode, or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. © 2010 Microchip Technology Inc. ...
Page 127
... U1BRG 0214 Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. TABLE 18-2: UART2 REGISTER MAP (NOT AVAILABLE ON dsPIC30F4012) SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name ...
Page 128
... NOTES: DS70135G-page 128 © 2010 Microchip Technology Inc. ...
Page 129
... Signaling via interrupt capabilities for all CAN receiver and transmitter error states • Programmable clock source © 2010 Microchip Technology Inc. dsPIC30F4011/4012 • Programmable link to input capture module (IC2, for both CAN1 and CAN2) for time-stamping and network synchronization • ...
Page 130
... RXF3 c Acceptance Filter e (1) RXF4 p t Acceptance Filter (1) RXF5 M Identifier (1) RXB1 A B Data Field Receive RERRCNT Error Counter TERRCNT Transmit ErrPas Error BusOff Counter Protocol Finite State Machine Bit Timing Bit Timing Logic Generator C1RX © 2010 Microchip Technology Inc. ...
Page 131
... Disable mode. The I/O pins will revert to normal I/O function when the module is in the Disable mode. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The module can be programmed to apply a low-pass filter function to the C1RX input line while the module or the CPU is in Sleep mode. The WAKFIL bit (C1CFG2< ...
Page 132
... End-of-Frame (EOF) field. Reading the RXxIF flag will indicate which receive buffer caused the interrupt. 19.4.6.2 Wake-up Interrupt The CAN module has woken up from Disable mode or the device has woken up from Sleep mode. © 2010 Microchip Technology Inc. ...
Page 133
... TXABT (C1TXxCON<6>), TXLARB (C1TXxCON<5>) and TXERR (C1TXxCON<4>) flag automatically cleared. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Setting TXREQ bit simply flags a message buffer as enqueued for transmission. When the module detects an available bus, it begins transmitting the message which has been determined to have the highest priority. ...
Page 134
... definition, the nominal bit time has a minimum and a maximum the minimum nominal bit time is 1 μsec, corresponding to a maximum bit rate of 1 MHz. Phase Phase Segment 1 Segment 2 Sample Point Figure 19-2. . Also, by definition, Q Sync © 2010 Microchip Technology Inc. ...
Page 135
... SEG1PH<2:0> (C1CFG2<5:3>), and Phase2 Seg is initialized by setting SEG2PH<2:0> (C1CFG2<10:8>). The following requirement must be fulfilled while setting the lengths of the phase segments: Propagation Segment + Phase1 Seg > = Phase2 Seg © 2010 Microchip Technology Inc. dsPIC30F4011/4012 19.6.5 SAMPLE POINT The sample point is the point of time at which the bus ...
Page 136
TABLE 19-1: CAN1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1RXF0SID 0300 — — — C1RXF0EIDH 0302 — — — — C1RXF0EIDL 0304 Receive Acceptance Filter 0 Extended Identifier<5:0> C1RXF1SID 0308 — — ...
Page 137
TABLE 19-1: CAN1 REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 C1TX1B2 0358 Transmit Buffer 1 Byte 3 C1TX1B3 035A Transmit Buffer 1 Byte 5 C1TX1B4 035C Transmit Buffer 1 Byte 7 C1TX1CON ...
Page 138
... NOTES: DS70135G-page 138 © 2010 Microchip Technology Inc. ...
Page 139
... The ADC module has a unique REF REF feature of being able to operate while the device is in Sleep mode. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • ...
Page 140
... AN5 AN8 AN0 AN1 AN2 AN3 AN3 AN4 AN4 AN5 AN5 AN6 (1) AN6 AN7 (1) AN7 (1) AN8 AN8 AN1 Note 1: Not available on dsPIC30F4012 devices. DS70135G-page 140 + CH1 ADC S/H - 10-bit Result + CH2 S/H - 16-word, 10-bit Dual Port + CH3 S/H - CH1,CH2, CH3,CH0 Sample/Sequence ...
Page 141
... The channels are then converted sequentially. Obviously, if there is only 1 channel selected, the SIMSAM bit is not applicable. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 The CHPS<1:0> bits select how many channels are sampled. This selection can vary from channels. ...
Page 142
... AD . The source of the A/D CONVERSION CLOCK * (0.5 * (ADCS<5:0> – time AD = 5V). Refer to Section 24.0 DD for minimum T under AD A/D CONVERSION CLOCK CALCULATION T = 154 nsec nsec (30 MIPS – 154 nsec = 2 • – nsec = 8. (ADCS<5:0> nsec = ( 165 nsec © 2010 Microchip Technology Inc. ...
Page 143
... T AD 500 ksps Up to 256. 300 ksps Note 1: External V - and V + pins must be used for correct operation. See REF REF circuit. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Table 20-1 Max. V Temperature S DD 500Ω 4.5V -40°C to +85°C to 5.5V ANx 500Ω 4.5V -40° ...
Page 144
... Sequential sampling must be used in this configuration to allow adequate sampling time on each input μF 0.1 μF 0.01 μ μF 0.1 μF 0.01 μF Multiple Analog Inputs © 2010 Microchip Technology Inc. ...
Page 145
... ADCS<5:0> control bits in the ADCON3 register • Configure the sampling time writing: SAMC<4:0> = 00010 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 20.7.3 600 ksps CONFIGURATION GUIDELINE The configuration for 600 ksps operation is dependent on whether a single input pin sampled or whether multiple pins are to be sampled ...
Page 146
... Refer to “Electrical Characteristics” requirements. ) impedance ≤ 250Ω Sampling Switch LEAKAGE V = 0.6V T ±500 nA period of sampling AD Section 24.0 for T and sample time AD ≤ 3 kΩ HOLD = DAC Capacitance = 4 negligible if Rs ≤ 5 kΩ. PIN © 2010 Microchip Technology Inc. ...
Page 147
... Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer 0 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 If the A/D interrupt is enabled, the device wakes up from Sleep. If the A/D interrupt is not enabled, the ADC module is then turned off, although the ADON bit remains set ...
Page 148
... The R component should be selected to ensure that the sampling time requirements are satisfied. Any external components connected (via high-impedance analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. © 2010 Microchip Technology Inc. as ESD SS ...
Page 149
... Legend uninitialized bit; — = unimplemented bit, read as ‘0’ Note 1: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. 2: These bits are not available on dsPIC30F4012 devices. Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — ...
Page 150
... NOTES: DS70135G-page 150 © 2010 Microchip Technology Inc. ...
Page 151
... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 21.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 152
... The dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as a system clock, as well as a Real-Time Clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70135G-page 152 Description (1) (2) (1) (1) (1) (3) /4 output OSC (3) © 2010 Microchip Technology Inc. ...
Page 153
... FIGURE 21-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 POR Done SOSCO 32 kHz LP Oscillator SOSCI Internal Fast RC Oscillator (FRC) © 2010 Microchip Technology Inc. dsPIC30F4011/4012 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Primary Oscillator Stability Detector Oscillator Start-up Clock ...
Page 154
... OST OSC2 FPR1 FPR0 Function CLKO CLKO OSC2 0 0 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 0 OSC2 — — (Notes 1, 2) — — (Notes 1, 2) — — (Notes 1, 2) © 2010 Microchip Technology Inc. ...
Page 155
... OSCTUN functionality has been provided to help customers compensate temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 TABLE 21-4: TUN<3:0> Bits 0111 0110 0101 0100 ...
Page 156
... To write to the OSCCON high byte, the following instructions must be executed without any other instructions in between: Byte Write 0x78 to OSCCON high Byte Write 0x9A to OSCCON high Byte Write is allowed for one instruction cycle. Write the desired value or use bit manipulation instruction. © 2010 Microchip Technology Inc. ...
Page 157
... Detect V DD Brown-out Reset BOREN Trap Conflict Illegal Opcode/ Uninitialized W Register © 2010 Microchip Technology Inc. dsPIC30F4011/4012 21.3.1 POR: POWER-ON RESET A power-on event generates an internal POR pulse when a V rise is detected. The Reset pulse occurs at DD the POR circuit threshold voltage (V inally 1 ...
Page 158
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL RESET FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL RESET DS70135G-page 158 T OST T PWRT T OST T PWRT T OST T PWRT ) DD ): CASE CASE 2 DD © 2010 Microchip Technology Inc. ...
Page 159
... Note: The BOR voltage trip points indicated here are nominal values provided for design guidance only. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FOS<1:0> and FPR< ...
Page 160
... Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70135G-page 160 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( © 2010 Microchip Technology Inc. ...
Page 161
... These are: Sleep and Idle. The format of the PWRSAV instruction is as follows: PWRSAV <parameter> where, ‘parameter’ defines Idle or Sleep mode. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 21.5.1 SLEEP MODE In Sleep mode, the clock to the CPU and peripherals is shut down on-chip oscillator is being used shut down ...
Page 162
... For additional information, please refer specifications of the device. Note: If the code protection Configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V to the programming ≥ 4.5V. DD © 2010 Microchip Technology Inc. ...
Page 163
... MPLAB IDE. These pin pairs are named EMUD/EMUC, EMUD1/ EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 In each case, the selected EMUD pin is the emulation/ debug data line and the EMUC pin is the emulation/ debug clock line ...
Page 164
TABLE 21-7: SYSTEM INTEGRATION REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name RCON 0740 TRAPR IOPUWR BGST — OSCCON 0742 TUN3 TUN2 COSC<1:0> TUN1 Legend: — = unimplemented bit, read as ‘0’ Note ...
Page 165
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 166
... DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate OA, OB, SA, SB Program Counter PC 10-bit signed literal ∈ {-512...511} Slit10 16-bit signed literal ∈ {-32768...32767} Slit16 6-bit signed literal ∈ {-16...16} Slit6 DS70135G-page 166 Description © 2010 Microchip Technology Inc. ...
Page 167
... Y Data Space Prefetch Address register for DSP instructions Wy ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y Data Space Prefetch Destination register for DSP instructions ∈ {W4..W7} Wyd © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Description DS70135G-page 167 ...
Page 168
... Branch if Accumulator A overflow Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> © 2010 Microchip Technology Inc Status Flags cycles Affected 1 1 OA, OB, SA DC ...
Page 169
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2010 Microchip Technology Inc. dsPIC30F4011/4012 # of Description words Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 170
... Move Move Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) Prefetch and store accumulator © 2010 Microchip Technology Inc Status Flags cycles Affected ...
Page 171
... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2010 Microchip Technology Inc. dsPIC30F4011/4012 # of Description words Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 172
... Wd = lit5 – Wb – ( nibble swap byte swap Wn Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-Extend Ws © 2010 Microchip Technology Inc Status Flags cycles Affected ...
Page 173
... MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits © 2010 Microchip Technology Inc. dsPIC30F4011/4012 23.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
Page 174
... Support for the entire device instruction set ® standard HEX • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility © 2010 Microchip Technology Inc. ...
Page 175
... Microchip Technology Inc. dsPIC30F4011/4012 23.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- ...
Page 176
... This usually includes a single application and debug capability, all for DDMAX on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. ® L security ICs, CAN ® © 2010 Microchip Technology Inc. ...
Page 177
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 (except V and MCLR) (Note 1) ...
Page 178
... Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +150 °C -40 — +125 ° INT – T )/θ Typ Max Unit Notes 41 — °C — °C — °C — °C — °C/W 1 © 2010 Microchip Technology Inc. ...
Page 179
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. 3: This is the limit to which V DD © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 180
... OSC1 DD 0.128 MIPS LPRC (512 kHz) (1.8 MIPS) FRC (7.37 MHz) 4 MIPS 10 MIPS 20 MIPS 30 MIPS . DD © 2010 Microchip Technology Inc. ...
Page 181
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with core off, clock on and all modules turned off. IDLE © 2010 Microchip Technology Inc. dsPIC30F4011/4012 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ≤ ...
Page 182
... PD (3) Base power-down current Watchdog Timer current: ΔI (3) WDT Timer1 w/32 kHz crystal: ΔI ( (3) BOR on: ΔI BOR © 2010 Microchip Technology Inc. ...
Page 183
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified lev- els represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 5: Negative current is defined as current sourced by the pin. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 184
... Industrial A ≤ +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode C™ mode (Device not in Brown-out Reset) © 2010 Microchip Technology Inc. ...
Page 185
... EB DD Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. 2: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature A -40°C ≤ T ...
Page 186
... Load Condition 2 – for OSC2 Pin 464Ω for all pins except OSC2 for OSC2 output OS20 OS30 OS30 OS25 OS40 ≤ +85°C for Industrial A ≤ +125°C for Extended A Section 24.1 “ OS31 OS31 OS41 © 2010 Microchip Technology Inc. ...
Page 187
... Measurements are taken ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 T © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40° ...
Page 188
... V = 4 ≤ +85° 3 ≤ +125° 3 ≤ +85° 4 ≤ +125° 4 ≤ +85° 3 ≤ +85° 4 ≤ +125° 4 © 2010 Microchip Technology Inc. ...
Page 189
... Oscillator T CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F © 2010 Microchip Technology Inc. dsPIC30F4011/4012 MIPS MIPS (2) (μsec) (3) w/o PLL w/PLL x4 20.0 0.05 — 1.0 1.0 4.0 0.4 2.5 10.0 0.16 6.25 — ...
Page 190
... DD ≤ +85°C for Industrial ≤ +125°C for Extended Conditions ≤ +85° 3.0-5. ≤ +125° 3.0-5. ≤ +85°C for Industrial ≤ +125°C for Extended Conditions V = 5.0V, ±10 3.3V, ±10 2.5V DD © 2010 Microchip Technology Inc. ...
Page 191
... These parameters are asynchronous events not related to any internal clock edges 2: Measurements are taken in RC mode and EC mode where CLKO output These parameters are characterized but not tested in manufacturing. 4: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 DI35 DI40 New Value DO31 DO32 for load ...
Page 192
... TIMER TIMING CHARACTERISTICS SY12 V DD MCLR Internal POR SY11 PWRT Time-out SY30 Oscillator Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to the Figure 24-2 for load conditions. DS70135G-page 192 SY10 SY20 SY13 SY13 © 2010 Microchip Technology Inc. ...
Page 193
... BGAP Start-up Time Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 194
... CY 10 — — 10 — — — — CY Greater of: — — 40)/ — — DC — 50 0.5 T — 1 Tx20 Units Conditions ns Must also meet parameter TA15 Must also meet parameter TA15 — prescale value (1, 8, 64, 256) ns kHz — © 2010 Microchip Technology Inc. ...
Page 195
... TxCK Low Time TC15 TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment © 2010 Microchip Technology Inc. dsPIC30F4011/4012 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T Min Typ Synchronous, 0 ...
Page 196
... CY with prescaler — CY with prescaler 0.5 T — CY TQ20 ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions — ns Must also meet parameter TQ15 — ns Must also meet parameter TQ15 — © 2010 Microchip Technology Inc. ...
Page 197
... TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 IC10 IC11 IC15 for load conditions. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) -40°C ≤ T ...
Page 198
... T Operating temperature -40°C ≤ T (2) Min Typ Max Units — — — ns — — — ns ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions See parameter DO32 See parameter DO31 © 2010 Microchip Technology Inc. ...
Page 199
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2010 Microchip Technology Inc. dsPIC30F4011/4012 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 200
... T Operating temperature -40°C ≤ T (1) (2) Min Typ Max Units — — — ns — — — ns — — — — ns ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions See parameter DO32 See parameter DO31 © 2010 Microchip Technology Inc. ...