DSPIC33FJ128GP306A-I/PT Microchip Technology, DSPIC33FJ128GP306A-I/PT Datasheet - Page 176

IC DSPIC MCU/DSP 128K 64-TQFP

DSPIC33FJ128GP306A-I/PT

Manufacturer Part Number
DSPIC33FJ128GP306A-I/PT
Description
IC DSPIC MCU/DSP 128K 64-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP306A-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Core Frequency
40MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
53
Flash Memory Size
128KB
Supply Voltage Range
3V To 3.6V
Rohs Compliant
No
Package
64TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
I2C/SPI/UART
On-chip Adc
18-chx10-bit|18-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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dsPIC33FJXXXGPX06A/X08A/X10A
14.1
REGISTER 14-1:
DS70593B-page 176
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-8
bit 7
bit 6-5
bit 4
bit 3
bit 2-0
Note 1: Timer selections may vary. Refer to the device data sheet for details.
ICTMR
R/W-0
U-0
Input Capture Registers
(1)
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1 = Input capture module will halt in CPU Idle mode
0 = Input capture module will continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bits
1 = TMR2 contents are captured on capture event
0 = TMR3 contents are captured on capture event
ICI<1:0>: Select Number of Captures per Interrupt bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
ICM<2:0>: Input Capture Mode Select bits
111 = Input capture functions as interrupt pin only when device is in Sleep or Idle mode
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge
100 = Capture mode, every 4th rising edge
011 = Capture mode, every rising edge
010 = Capture mode, every falling edge
001 = Capture mode, every edge (rising and falling)
000 = Input capture module turned off
R/W-0
U-0
ICxCON: INPUT CAPTURE x CONTROL REGISTER
(Rising edge detect only, all other control bits are not applicable.)
(ICI<1:0> bits do not control interrupt generation for this mode.)
ICI<1:0>
W = Writable bit
‘1’ = Bit is set
ICSIDL
R/W-0
R/W-0
R-0, HC
ICOV
U-0
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0, HC
ICBNE
U-0
R/W-0
U-0
 2009 Microchip Technology Inc.
x = Bit is unknown
ICM<2:0>
R/W-0
U-0
R/W-0
U-0
bit 8
bit 0

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