ATMEGA16-16PU Atmel, ATMEGA16-16PU Datasheet
ATMEGA16-16PU
Specifications of ATMEGA16-16PU
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ATMEGA16-16PU Summary of contents
Page 1
... ATmega16L – 4.5 - 5.5V for ATmega16 • Speed Grades – MHz for ATmega16L – MHz for ATmega16 • Power Consumption @ 1 MHz, 3V, and 25°C for ATmega16L – Active: 1.1 mA – Idle Mode: 0.35 mA – Power-down Mode: < 1 µA ® 8-bit Microcontroller (1) ...
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... Pin Figure 1. Pinout ATmega16 Configurations Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. ATmega16(L) 2 PDIP (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 ...
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... Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed. Block Diagram Figure 2 ...
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... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16 is a powerful microcontroller that provides a highly-flexible and cost-effec- tive solution to many embedded control applications. The ATmega16 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...
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... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16 as listed on 58. Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATmega16( 2466R–AVR–06/08 ...
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... These code examples assume that the part specific header file is included before Examples compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling compiler dependent. Please confirm with the C Compiler documen- tation for more details. 2466R–AVR–06/08 ATmega16(L) 7 ...
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... Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every program memory address contains a 16- or 32-bit instruction. ATmega16(L) 8 Data Bus 8-bit Program ...
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... The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. 2466R–AVR–06/ R/W R/W R/W R/W R ATmega16( SREG R/W R/W R ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATmega16(L) 10 ⊕ V 2466R–AVR–06/08 ...
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... R13 General R14 Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 4, each register is also assigned a data memory address, mapping them ATmega16(L) 0 Addr. $00 $01 $02 $0D $0E $0F $10 $11 $1A X-register Low Byte $1B X-register High Byte $1C Y-register Low Byte $1D ...
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... The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit Read/Write Initial Value ATmega16( R27 ($1B) 15 ...
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... Instruction Fetch 2nd Instruction Fetch 3rd Instruction Fetch 4th Instruction Fetch shows the internal timing concept for the Register File single clock cycle an ALU clk CPU Total Execution Time Result Write Back for details. ATmega16( “Interrupts” on page T4 T4 “Memory Program- 45 ...
Page 14
... SREG; /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ ATmega16(L) 14 “Boot Loader Support – Read-While-Write Self- 246. ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 2466R–AVR–06/08 ; set global interrupt enable ATmega16(L) 15 ...
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... Program section and Application Program section. Memory The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega16 Pro- gram Counter (PC bits wide, thus addressing the 8K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in 246 ...
Page 17
... X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega16 are all accessible through all these addressing modes. The Register File is described in Figure 9. Data Memory Map 2466R– ...
Page 18
... SRAM access is performed in two clk Figure 10. On-chip Data SRAM Access Cycles EEPROM Data The ATmega16 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at Memory least 100,000 write/erase cycles ...
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... Read/Write Initial Value • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address The EEPROM Address Registers 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511 ...
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... The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling inter- rupts globally) so that no interrupts will occur during execution of these functions. The examples ATmega16(L) 20 Number of Calibrated RC Symbol Oscillator Cycles 1 ...
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... Start eeprom write by setting EEWE sbi EECR,EEWE ret /* Wait for completion of previous write */ while(EECR & (1<<EEWE Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); ATmega16(L) 21 ...
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... An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec- ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. ATmega16(L) 22 EEARH, r18 EEARL, r17 ...
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... I/O Memory The I/O space definition of the ATmega16 is shown in All ATmega16 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions, transferring data between the 32 general purpose working regis- ters and the I/O space. I/O Registers within the address range $00 - $1F are directly bit- accessible using the SBI and CBI instructions ...
Page 24
... The dedicated clock domain allows using this ASY Timer/Counter as a real-time counter even when the device is in sleep mode. ATmega16(L) 24 presents the principal clock systems in the AVR and their distribution. All of the clocks 32. The clock systems are detailed ...
Page 25
... For all fuses “1” means unprogrammed while “0” means programmed. 299. = 5.0V) Typ Time-out ( ATmega16(L) CKSEL3..0 1111 - 1010 1001 1000 - 0101 0100 - 0001 0000 = 3.0V) Number of Cycles CC 4 (4,096 64K (65,536) Figure 12. Either a quartz crystal or a Table “ATmega16 Typ- 25 ...
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... Figure 12. Crystal Oscillator Connections The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4. Crystal Oscillator Operating Modes CKOPT Note: ATmega16( Frequency Range CKSEL3..1 (MHz) (1) 101 0.4 - 0.9 110 0 ...
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... These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. ATmega16(L) Additional Delay from Reset ( ...
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... Figure 13. External RC Configuration The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 7. External RC Oscillator Operating Modes ATmega16(L) 28 Figure 12. By programming the CKOPT Fuse, the user can enable internal ...
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... The device is shipped with this option selected. Start-up Time from Additional Delay Power-down and Power-save The device is shipped with this option selected. ATmega16(L) = 5.0V) Recommended Usage – BOD enabled Fast rising power Slowly rising power Fast rising power or BOD enabled Table 9 ...
Page 30
... If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal fre- quency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 11. Table 11. Internal RC Oscillator Frequency Range. OSCCAL Value $00 $7F $FF ATmega16( CAL7 CAL6 CAL5 CAL4 ...
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... Start-up Time from Additional Delay Power-down and Power-save The Timer/Counter Oscillator uses the same type of crystal oscillator as Low-Frequency Oscillator and the internal capacitors have the same nominal value of 36 pF. ATmega16(L) from Reset (V = 5.0V) Recommended Usage CC – BOD enabled 4.1 ms Fast rising power ...
Page 32
... To avoid the MCU entering the sleep mode unless it is the programmers purpose recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. ATmega16(L) 32 presents the different clock systems in the ATmega16, and their distribu ...
Page 33
... Timer/Counter2 if clocked asynchronously. 2466R–AVR–06/08 and clk , while allowing the other clocks to run. CPU FLASH , clk I/O “Clock Sources” on page , allowing operation only of asynchronous ASY ATmega16(L) , and clk , while allowing the CPU FLASH “External Interrupts” on page 68 25. 33 ...
Page 34
... Noise X Redu- ction Power Down Power Save (1) Standby Exten- ded (1) Standby Notes: 1. External Crystal or resonator selected as clock source bit in ASSR is set. 3. Only INT2 or level interrupt INT1 and INT0. ATmega16(L) 34 Oscillators Main Clock Timer Osc. clk Source Enabled Enabled ADC ASY ( ( (2) (2) ...
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... ADC clock (clk I/O “Digital Input Enable and Sleep Modes” on page 54 /2, the input buffer will use excessive power. CC ATmega16(L) “Analog to Digital Converter” on page 204 for details on how to for details on how to “Internal Volt- ) are stopped, the input buffers of the ...
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... Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. ATmega16(L) 36 2466R–AVR–06/08 ...
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... CKSEL Fuses. The different selec- tions for the delay period are presented in Reset Sources The ATmega16 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • ...
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... V antees that a Brown-out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega16L and BODLEVEL = 0 for ATmega16. BODLEVEL = 1 is not applicable for ATmega16. DATA BUS MCU Control and Status ...
Page 39
... Table 15. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level POT RST RESET t TOUT TIME-OUT INTERNAL RESET V POT V CC RESET TIME-OUT INTERNAL RESET ATmega16(L) is below the detection level. The RST t TOUT 39 ...
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... Time-out period t Figure 18. External Reset During Operation Brown-out Detection ATmega16 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V ing operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed), or 4.0V (BODLEVEL programmed) ...
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... Reset Flags. 2466R–AVR–06/08 for details on operation of the Watchdog Timer JTD ISC2 – JTRF R/W R ATmega16( WDRF BORF EXTRF PORF MCUCSR R/W R/W R/W R/W See Bit Description . Refer to TOUT 41 ...
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... Internal Voltage ATmega16 features an internal bandgap reference. This reference is used for Brown-out Detec- Reference tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference The voltage reference has a start-up time that may influence the way it should be used. The ...
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... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled ...
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... Turn off WDT ldi out ret C Code Example void WDT_off(void Reset WDT*/ _WDR(); /* Write logical one to WDTOE and WDE */ WDTCR |= (1<<WDTOE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } ATmega16(L) 44 r16, WDTCR WDTCR, r16 r16, (0<<WDE) WDTCR, r16 2466R–AVR–06/08 ...
Page 45
... Interrupts This section describes the specifics of the interrupt handling as performed in ATmega16. For a general explanation of the AVR interrupt handling, refer to page 13. Interrupt Vectors in ATmega16 Table 18. Reset and Interrupt Vectors Vector No Notes: Table 19 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations ...
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... Table 19. Reset and Interrupt Vectors Placement BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16 is: Address $000 $002 $004 $006 $008 $00A $00C $00E $010 $012 $014 $016 $018 $01A $01C $01E $020 ...
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... RESET: ldi r16,high(RAMEND) ; Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx ATmega16(L) Comments ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler Comments ; IRQ0 Handler ; IRQ1 Handler ; ; Store Program Memory Ready Handler ...
Page 48
... Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below ATmega16( ...
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... Enable change of interrupt vectors ldi r16, (1<<IVCE) out GICR, r16 ; Move interrupts to boot Flash section ldi r16, (1<<IVSEL) out GICR, r16 ret /* Enable change of interrupt vectors */ GICR = (1<<IVCE); /* Move interrupts to boot Flash section */ GICR = (1<<IVSEL); ATmega16(L) 49 ...
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... Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Ports as General The ports are bi-directional I/O ports with optional internal pull-ups. description of one I/O-port pin, here generically called Pxn. Digital I/O ATmega16(L) 50 and Ground as indicated in CC for a complete list of parameters. Pxn ...
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... SLEEP CONTROL clk : I/O CLOCK I/O 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. 66, the DDxn bits are accessed at the DDRx I/O address, the ATmega16( DDxn Q CLR RESET Q ...
Page 52
... LATCH” signal. The signal value is latched when the system clock goes low clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows t between ½ and 1½ system clock period depending upon the time of assertion. ATmega16(L) 52 summarizes the control signals for the pin value. PUD ...
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... INSTRUCTIONS SYNC LATCH 2466R–AVR–06/08 Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive edge of the through the synchronizer is one system clock period. pd r16 out PORTx, r16 PINxn r17 ATmega16(L) 0xFF nop in r17, PINx 0x00 t pd 0xFF 53 ...
Page 54
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the External Inter- rupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. ATmega16(L) 54 (1) r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) r17,(1< ...
Page 55
... DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk and PUD are common to all ports. All other signals are unique for each pin. ATmega16(L) Figure 23 can be overridden by alter- PUOExn PUOVxn ...
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... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATmega16(L) 56 summarizes the function of the overriding signals. The pin and port indexes from Full Name ...
Page 57
... ADC2 (ADC input channel 2) ADC1 (ADC input channel 1) ADC0 (ADC input channel 0) and Table 24 relate the alternate functions of Port A to the overriding signals shown in 55. PA7/ADC7 PA6/ADC6 – ADC7 INPUT ADC6 INPUT ATmega16( ACME PUD PSR2 PSR10 R/W R/W R/W R Table PA5/ADC5 PA4/ADC4 ...
Page 58
... Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced by the SPI input, the pull-up can still be controlled by the PORTB6 bit. ATmega16(L) 58 PA3/ADC3 PA2/ADC2 ...
Page 59
... Figure 26 on page while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. 2466R–AVR–06/08 and Table 27 relate the alternate functions of Port B to the overriding signals shown in 55. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, ATmega16(L) 59 ...
Page 60
... Table 27. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega16(L) 60 PB7/SCK PB6/MISO SPE • MSTR SPE • MSTR PORTB7 • PUD PORTB6 • PUD SPE • MSTR SPE • MSTR 0 0 SPE • MSTR SPE • ...
Page 61
... TOSC1 (Timer Oscillator Pin 1) TDI (JTAG Test Data In) TDO (JTAG Test Data Out) TMS (JTAG Test Mode Select) TCK (JTAG Test Clock) SDA (Two-wire Serial Bus Data Input/Output Line) SCL (Two-wire Serial Bus Clock Line) ATmega16(L) Table 28. If the JTAG interface is enabled, 61 ...
Page 62
... Figure 26 on page Table 29. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega16(L) 62 and Table 30 relate the alternate functions of Port C to the overriding signals shown in 55. PC7/TOSC2 PC6/TOSC1 AS2 AS2 0 0 AS2 AS2 ...
Page 63
... ICP1 (Timer/Counter1 Input Capture Pin) OC1A (Timer/Counter1 Output Compare A Match Output) OC1B (Timer/Counter1 Output Compare B Match Output) INT1 (External Interrupt 1 Input) INT0 (External Interrupt 0 Input) TXD (USART Output Pin) RXD (USART Input Pin) ATmega16(L) (1) PC1/SDA PC0/SCL TWEN TWEN PORTC1 • PUD PORTC0 • ...
Page 64
... PORTD0 bit. Table 32 Figure 26 on page Table 32. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega16(L) 64 and Table 33 relate the alternate functions of Port D to the overriding signals shown in 55. PD7/OC2 PD6/ICP1 ...
Page 65
... PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 2466R–AVR–06/08 PD3/INT1 PD2/INT0 INT1 ENABLE INT0 ENABLE 1 1 INT1 INPUT INT0 INPUT – – ATmega16(L) PD1/TXD PD0/RXD TXEN RXEN 0 PORTD0 • PUD TXEN RXEN 1 0 TXEN 0 TXD – RXD – – 65 ...
Page 66
... Initial Value Port B Data Register – PORTB Bit Read/Write Initial Value Port B Data Direction Register – DDRB Bit Read/Write Initial Value Port B Input Pins Address – PINB Bit Read/Write Initial Value ATmega16( PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 R/W R/W R/W R/W 0 ...
Page 67
... PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N/A ATmega16( PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 ...
Page 68
... Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 34. Interrupt 1 Sense Control ISC11 ATmega16(L) 68 “Electrical Characteristics” on page 24. If the level is sampled twice by the Watchdog Oscillator clock but SM2 ...
Page 69
... Table 36 will generate an interrupt. Shorter pulses are not guaranteed to Parameter Minimum pulse width for asynchronous external interrupt INT1 INT0 INT2 – R/W R/W R ATmega16( WDRF BORF EXTRF PORF MCUCSR R/W R/W R/W R/W See Bit Description Condition Min Typ Max – ...
Page 70
... Note that when entering some sleep modes with the INT2 interrupt disabled, the input buffer on this pin will be disabled. This may cause a logic change in internal signals which will set the INTF2 Flag. See Modes” on page 54 ATmega16( ...
Page 71
... The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). 2466R–AVR–06/08 “Pinout ATmega16” on page “8-bit Timer/Counter Register Description” on page TCCRn count ...
Page 72
... Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of ATmega16(L) 72 for details. The compare match event will also set the Compare Flag (OCF0) Table 37 are also used extensively throughout the document ...
Page 73
... A CPU write overrides (has priority over) all counter clear or T0 76. (See “Modes of Operation” on page shows a block diagram of the output compare unit. DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega16(L) 76.). TCNTn OCFn (Int.Req.) OCn COMn1:0 73 ...
Page 74
... Only the parts of the general I/O port Control Registers (DDR and PORT) that are affected by the COM01:0 bits are shown. When referring to the OC0 state, the reference is for the internal OC0 Register, not the OC0 pin System Reset occur, the OC0 Register is reset to “0”. ATmega16(L) 74 Figure 30 shows a simplified schematic of ...
Page 75
... For non-PWM modes, the action can be forced to have immediate effect by using the FOC0 strobe bits. 2466R–AVR–06/08 COMn1 Waveform COMn0 Generator FOCn clk I/O See “8-bit Timer/Counter Register Description” on page 83. Table 39 on page 84. For fast PWM mode, refer to Table 41 on page ATmega16( OCn PORT D Q DDR Table 40 on page 84. ...
Page 76
... OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have ATmega16(L) 76 74.). ...
Page 77
... OCn Figure 32. The TCNT0 value is in the timing diagram shown as a histo- TCNTn OCn OCn Period ATmega16(L) f clk_I/O ---------------------------------------------- - ⋅ ⋅ OCRn OCRn Interrupt Flag Set OCRn Update and ...
Page 78
... PWM mode. If the OCR0 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.) ATmega16(L) 78 Table 40 on page 84) ...
Page 79
... OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The 2466R–AVR–06/ Table 41 on page ATmega16(L) Figure 33. OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 84) ...
Page 80
... BOTTOM the OCn value at MAX must be correspond to the result of an up-counting Compare Match. • The Timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. ATmega16( clk_I ----------------- - ⋅ ...
Page 81
... Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. I/O Tn /8) I/O MAX - 1 shows the setting of OCF0 in all modes except CTC mode. ATmega16( therefore shown MAX BOTTOM BOTTOM + 1 /8) clk_I/O MAX BOTTOM BOTTOM + 1 81 ...
Page 82
... OCRn OCFn Figure 37 Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O clk clk (clk TCNTn (CTC) OCRn OCFn ATmega16(L) 82 I/O Tn /8) I/O OCRn - 1 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. /8) I/O Tn /8) I/O ...
Page 83
... PWM, Phase Correct 1 0 CTC 1 1 Fast PWM 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. ATmega16( WGM01 CS02 CS01 CS00 R/W ...
Page 84
... Note: Table 41 PWM mode. Table 41. Compare Output Mode, Phase Correct PWM Mode COM01 Note: ATmega16(L) 84 Table 39 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a COM00 Description 0 Normal port operation, OC0 disconnected. 1 Toggle OC0 on compare match 0 Clear OC0 on compare match ...
Page 85
... External clock source on T0 pin. Clock on rising edge TCNT0[7:0] R/W R/W R/W R OCR0[7:0] R/W R/W R/W R OCIE2 TOIE2 TICIE1 OCIE1A R/W R/W R/W R ATmega16( R/W R/W R/W R R/W R/W R/W R OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R TCNT0 OCR0 TIMSK 85 ...
Page 86
... Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. ATmega16( ...
Page 87
... The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 /clk I/O Synchronization < f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O ATmega16(L) /8, f /64, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative Edge Detector /256, or CLK_I/O Figure 38 ). The latch ...
Page 88
... The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. ATmega16(L) 88 Clear ...
Page 89
... I/O pins, are shown in bold. The device specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 2466R–AVR–06/08 Figure 1 on page 2. CPU accessible I/O Registers, including I/O 110. ATmega16(L) Figure 40. For the actual 89 ...
Page 90
... The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). put Compare Units” on page 98. Flag (OCF1A/B) which can be used to generate an output compare interrupt request. ATmega16(L) 90 Count Clear ...
Page 91
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Regis- ter. The assignment is dependent of the mode of operation. ATmega16(L) (See 91 ...
Page 92
... Timer Regis- ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. ATmega16(L) 92 (1) r16,TCNT1L ...
Page 93
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page 7. ATmega16(L) 93 ...
Page 94
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits Clock Sources located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see ATmega16(L) 94 (1) r18,SREG (1) 1. See “ ...
Page 95
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear “Modes of Operation” on page ATmega16(L) TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 101 ...
Page 96
... TOP value can be written to the ICR1 Register. When writing the ICR1 Register the High byte must be written to the ICR1H I/O loca- tion before the Low byte is written to ICR1L. ATmega16(L) 96 DATA BUS TEMP (8-bit) ...
Page 97
... Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 2466R–AVR–06/08 92. ATmega16(L) “Accessing 16-bit Registers” (Figure 38 on page 87). The edge detector is also 97 ...
Page 98
... CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte ATmega16(L) 98 (See “Modes of Operation” on page shows a block diagram of the output compare unit. The small “ ...
Page 99
... Normal mode. The OC1x Register keeps its value even when changing between waveform generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 2466R–AVR–06/08 92. ATmega16(L) “Accessing 16-bit Registers” 99 ...
Page 100
... PWM refer to 111. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. ATmega16(L) 100 COMnx1 Waveform COMnx0 ...
Page 101
... OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 45. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 2466R–AVR–06/08 100.) “Timer/Counter Timing Diagrams” on page Figure ATmega16(L) 108. 45. The counter value (TCNT1) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 101 ...
Page 102
... PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. ATmega16(L) 102 = f /2 when OCR1A is set to zero (0x0000). The waveform frequency is ...
Page 103
... OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). 2466R–AVR–06/ ATmega16(L) OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set OCnA Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 ...
Page 104
... The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter- rupt Flag will be set when a compare match occurs. ATmega16(L) 104 f clk_I/O ...
Page 105
... OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when 2466R–AVR–06/ ATmega16(L) OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set ...
Page 106
... The diagram includes non- inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes repre- sent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. ATmega16(L) 106 f OCnxPCPWM 48) ...
Page 107
... PWM mode. If the OCR1x is set equal to BOTTOM the 2466R–AVR–06/ shows the output generated is, in contrast to the phase correct mode, symmetrical f OCnxPFCPWM ATmega16(L) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) ...
Page 108
... Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 51 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams ATmega16(L) 108 Figure 49 I/O Tn /1) I/O OCRnx - 1 shows the same timing data, but with the prescaler enabled. ...
Page 109
... I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TCNTn TOP - 1 (FPWM) (if used as TOP) OCRnx Old OCRnx Value ATmega16(L) TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 New OCRnx Value TOP - 2 ...
Page 110
... OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Table 44. Compare Output Mode, non-PWM COM1A1/COM1B1 Table 45 mode. ATmega16(L) 110 COM1A1 COM1A0 ...
Page 111
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. “Phase Correct PWM Mode” on page 104. ATmega16(L) (1) Description Normal port operation, OC1A/OC1B disconnected. WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM13:0 settings, normal port operation, OCnA/OCnB disconnected ...
Page 112
... Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the location of these bits are compatible with previous versions of the timer. ATmega16(L) 112 Table 47. Modes of operation supported by the Timer/Counter (See “Modes of Operation” on page (1) WGM10 (PWM10) Timer/Counter Mode of Operation 0 Normal ...
Page 113
... I clk /64 (From prescaler) I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on T1 pin. Clock on falling edge External clock source on T1 pin. Clock on rising edge. ATmega16( WGM12 CS12 CS11 CS10 TCCR1B R/W R/W R/W R Figure 113 ...
Page 114
... CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Input Capture Register 1 – ICR1H and ICR1L Bit Read/Write Initial Value ATmega16(L) 114 TCNT1[15:8] ...
Page 115
... OCF2 TOV2 ICF1 OCF1A R/W R/W R/W R This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections. ATmega16( OCIE1B TOIE1 OCIE0 TOIE0 R/W R/W R/W R/W ...
Page 116
... TOV1 Flag is set when the timer overflows. Refer to behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow interrupt vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. ATmega16(L) 116 Table 47 on page 112 for the TOV1 Flag ...
Page 117
... Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac- tive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk 2466R–AVR–06/08 “Pinout ATmega16” on page “8-bit Timer/Counter Register Description” on page TCCRn count ...
Page 118
... T2 top ATmega16(L) 118 for details. The compare match event will also set the Compare Flag (OCF2) The counter reaches the BOTTOM when it becomes zero (0x00). The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence ...
Page 119
... A CPU write overrides (has priority over) all counter clear or T2 122. can be used for generating a CPU interrupt. TOV2 122). Figure 55 shows a block diagram of the output compare unit. DATA BUS OCRn = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega16(L) (“Modes of Operation” TCNTn OCFn (Int.Req.) OCxy COMn1:0 119 ...
Page 120
... Normal mode. The OC2 Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately. ATmega16(L) 120 2466R–AVR–06/08 ...
Page 121
... FOC2 strobe bits. 2466R–AVR–06/08 COMn1 Waveform COMn0 Generator FOCn clk I/O See “8-bit Timer/Counter Register Description” on page 128. Table 51 on page 129. For fast PWM mode, refer to Table 53 on page ATmega16(L) Figure 56 shows a simplified schematic OCn Pin OCn PORT ...
Page 122
... TOP value. However, changing the TOP to a value close to BOTTOM when the counter is run- ning with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current ATmega16(L) 122 121.). ...
Page 123
... OCn Figure 58. The TCNT2 value is in the timing diagram shown as a histo- TCNTn OCn OCn Period set each time the counter reaches MAX. If the inter- TOV2 ATmega16(L) f clk_I/O ---------------------------------------------- - ⋅ ⋅ OCRn Flag is set in the same timer clock cycle that the TOV2 ...
Page 124
... The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. ATmega16(L) 124 Table 52 on page 129) ...
Page 125
... Compare Match and hence the OCn that would have happened on the way up. 2466R–AVR–06/08 TCNTn OCn OCn Period 1 TOV2 f OCnPCPWM Figure 59 ATmega16(L) OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set (COMn1 (COMn1 set each time the counter reaches BOTTOM. The Table 53 on page 129). The actual OC2 ...
Page 126
... TOVn Figure 61 Figure 61. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 62 ATmega16(L) 126 contains timing data for basic Timer/Counter operation. The figure shows the I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ...
Page 127
... TCNTn (CTC) OCRn OCFn 2466R–AVR–06/08 I/O Tn /8) I/O OCRn - 1 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. /8) I/O Tn /8) I/O TOP - 1 ATmega16(L) OCRn OCRn + 1 OCRn Value TOP BOTTOM TOP /8) clk_I/O OCRn + 2 BOTTOM + 1 127 ...
Page 128
... These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. ATmega16(L) 128 7 6 ...
Page 129
... A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See 124 for more details. ATmega16(L) (1) “Fast PWM Mode” on page 123 (1) “Phase Correct PWM Mode” on page ...
Page 130
... Register – OCR2 Bit Read/Write Initial Value The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt generate a waveform output on the OC2 pin. ATmega16(L) 130 CS21 CS20 Description clock source (Timer/Counter stopped). ...
Page 131
... Write new values to TCNT2, OCR2, and TCCR2 switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. 2466R–AVR–06/ – – – – AS2 R ATmega16( TCN2UB OCR2UB TCR2UB ASSR When AS2 is I/O 131 ...
Page 132
... TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: ATmega16(L) 132 ) again becomes active, TCNT2 will read as the previous I/O 2466R– ...
Page 133
... PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. 2466R–AVR–06/ OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B R/W R/W R/W R OCF2 TOV2 ICF1 OCF1A OCF1B R/W R/W R/W R ATmega16( TOIE1 OCIE0 TOIE0 TIMSK R/W R/W R/W R TOV1 OCF0 TOV0 TIFR R/W R/W R/W R 133 ...
Page 134
... Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. ATmega16(L) 134 clk clk ...
Page 135
... Serial The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16 and peripheral devices or between several AVR devices. The ATmega16 SPI Peripheral includes the following features: Interface – SPI • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 136
... High periods: Longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to nate Port Functions” on page Table 55. SPI Pin Overrides Pin MOSI MISO SCK SS ATmega16(L) 136 MSB MASTER LSB MISO 8 BIT SHIFT REGISTER MOSI SPI SCK ...
Page 137
... For example if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. 2466R–AVR–06/08 See “Alternate Functions of Port B” on page 58 direction of the user defined SPI pins. ATmega16(L) for a detailed description of how to define the 137 ...
Page 138
... SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: ATmega16(L) 138 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPDR,r16 (1) ; ...
Page 139
... Read received data and return in r16,SPDR ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return data register */ return SPDR; 1. See “About Code Examples” on page 7. ATmega16(L) 139 ...
Page 140
... When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. ATmega16(L) 140 ...
Page 141
... Figure 68 Leading Edge 0 Rising 1 Falling Figure 67 Leading Edge 0 Sample 1 Setup SPR1 SPR0 ATmega16(L) for an example. The CPOL functionality is summa- Trailing Edge Falling Rising and Figure 68 for an example. The CPHA func- Trailing Edge Setup Sample SCK Frequency osc osc osc 128 ...
Page 142
... When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work lower. The SPI interface on the ATmega16 is also used for program memory and EEPROM download- ing or uploading. See SPI Data Register – SPDR ...
Page 143
... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega16(L) Trailing Edge SPI Mode Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 ...
Page 144
... Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode Overview A simplified block diagram of the USART transmitter is shown in Registers and I/O pins are shown in bold. Figure 69. USART Block Diagram Note: ATmega16(L) 144 (1) UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER ...
Page 145
... The XCK pin is only active when using Synchronous mode. Figure 70 2466R–AVR–06/08 shows a block diagram of the clock generation logic. ATmega16(L) Figure 69) if the Buffer Registers are 145 ...
Page 146
... However, the recovery units use a state machine that uses states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. Table 60 the UBRR value for each mode of operation using an internally generated clock source. ATmega16(L) 146 UBRR fosc UBRR+1 ...
Page 147
... BAUD BAUD BAUD 1. The baud rate is defined to be the transfer rate in bit per second (bps). System Oscillator clock frequency Figure 70 for details. depends on the stability of the system clock source therefore recommended to osc ATmega16(L) Equation for Calculating UBRR (1) Baud Rate Value f OSC ----------------------- - 1 ...
Page 148
... When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 72 optional. Figure 72. Frame Formats (IDLE ATmega16(L) 148 UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 71 shows, when UCPOL is zero the data will be changed at ris- illustrates the possible combinations of the frame formats ...
Page 149
... No transfers on the communication line (RxD or TxD). An IDLE line must be high. ⊕ … even n 1 – ⊕ … odd n 1 – Parity bit using even parity Parity bit using odd parity Data bit n of the character ATmega16(L) ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ d ...
Page 150
... A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The Data Bit CPU can load the transmit buffer by writing to the UDR I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new ATmega16(L) 150 (1) UBRRH, r17 UBRRL, r16 r16, (1< ...
Page 151
... UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; 1. See “About Code Examples” on page 7. ATmega16(L) 151 ...
Page 152
... UDRE is cleared by writing UDR. When interrupt-driven data transmission is used, the Data Register Empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new inter- rupt will occur once the interrupt routine terminates. ATmega16(L) 152 (1) UCSRB,TXB8 ...
Page 153
... The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing Transmitter and pending transmissions are completed, i.e., when the transmit Shift Register and transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no lon- ger override the TxD pin. 2466R–AVR–06/08 ATmega16(L) 153 ...
Page 154
... Get and return received data from buffer */ return UDR; } Note: The function simply waits for data to be present in the receive buffer by checking the RXC Flag, before reading the buffer and returning the value. ATmega16(L) 154 (1) r16, UDR ( See “About Code Examples” on page 7. ...
Page 155
... UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<PE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 7. ATmega16(L) 155 ...
Page 156
... The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. ATmega16(L) 156 and “Parity Checker” on page 156. 2466R– ...
Page 157
... Double Speed mode (indicated with sample numbers inside boxes on the 2466R–AVR–06/08 (1) sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush (1) unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR; 1. See “About Code Examples” on page 7. IDLE ATmega16(L) START Figure 73 BIT 157 ...
Page 158
... A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in (C) marks a stop bit of full length. The early start bit detection influences the operational range of the receiver. ATmega16(L) 158 Figure ...
Page 159
... D R (%) R (%) slow fast 5 94.12 105.66 6 94.92 104.92 7 95.52 104.35 ATmega16( ------------------------------------------ - D S ⋅ – ----------------------------------- ( ) for Normal Speed and for Normal Speed and M Max Total Recommended Max Error (%) Receiver Error (%) +6 ...
Page 160
... The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible. ATmega16(L) 160 D R ...
Page 161
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit. The MPCM bit shares the same I/O location as the TXC Flag and this might accidentally be cleared when using SBI or CBI instructions. 2466R–AVR–06/08 ATmega16(L) 161 ...
Page 162
... UBRRH Register contents. If the register location was read in previous system clock cycle, read- ing the register in the current clock cycle will return the UCSRC contents. Note that the timed sequence for reading the UCSRC is an atomic operation. Interrupts must therefore be controlled (for example by disabling interrupts globally) during the read operation. ATmega16(L) 162 (1) (1) 1. See “ ...
Page 163
... SBIS), since these also will change the state of the FIFO. 2466R–AVR–06/08 (1) ; Read UCSRC in r16,UBRRH in r16,UCSRC ret (1) unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; 1. See “About Code Examples” on page RXB[7:0] TXB[7:0] R/W R/W R/W R ATmega16( UDR (Read) UDR (Write) R/W R/W R/W R 163 ...
Page 164
... This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from effectively dou- bling the transfer rate for asynchronous communication. ATmega16(L) 164 7 6 ...
Page 165
... RXB8 is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDR. 2466R–AVR–06/08 “Multi-processor Communication Mode” on page RXCIE TXCIE UDRIE RXEN TXEN R/W R/W R/W R ATmega16(L) 161 UCSZ2 RXB8 TXB8 UCSRB R/W R 165 ...
Page 166
... If a mismatch is detected, the PE Flag in UCSRA will be set. Table 64. UPM Bits Settings UPM1 • Bit 3 – USBS: Stop Bit Select This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 65. USBS Bit Settings ATmega16(L) 166 URSEL ...
Page 167
... TxD Pin) Rising XCK Edge Falling XCK Edge URSEL – – – UBRR[7: R R/W R/W R/W R ATmega16(L) UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge UBRR[11: ...
Page 168
... Max 62.5 kbps 125 kbps 1. UBRR = 0, Error = 0.0% ATmega16(L) 168 159). The error values are calculated using the following equation: BaudRate ⎛ Error[%] ------------------------------------------------------- - 1 = ⎝ BaudRate f = 1.8432 MHz osc U2X = 0 U2X = 1 Error UBRR ...
Page 169
... ATmega16( 7.3728 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0. ...
Page 170
... Max 0.5 Mbps 1. UBRR = 0, Error = 0.0% ATmega16(L) 170 11.0592 f = osc U2X = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% ...
Page 171
... Mbps 1.152 Mbps ATmega16( 20.0000 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 ...
Page 172
... TWI Terminology The following definitions are frequently encountered in this section. Table 72. TWI Terminology Term Master Slave Transmitter Receiver ATmega16(L) 172 Device 1 Device 3 Device 2 Description The device that initiates and terminates a transmission. The Master also generates the SCL clock. The device addressed by a Master. ...
Page 173
... START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. 2466R–AVR–06/08 Figure 76, both bus lines are connected to the positive supply voltage through “Two-wire Serial Interface Characteristics” on page SDA SCL Data Stable Data Change ATmega16(L) 294. Two Data Stable 173 ...
Page 174
... Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several Slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. Figure 79. Address Packet Format SDA SCL ATmega16(L) 174 START STOP START Addr MSB 1 ...
Page 175
... Data MSB 1 2 SLA+R/W shows a typical data transmission. Note that several data bytes can be transmitted Addr MSB Addr LSB R/W ACK START SLA+R/W ATmega16(L) Data LSB ACK STOP, REPEATED Data Byte START or Next Data MSB Data LSB ACK ...
Page 176
... Masters are allowed to generate a clock signal until the end of the current data or address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several Masters are trying to address the same Slave, arbitration will continue into the data packet. ATmega16(L) 176 TA low ...
Page 177
... SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 2466R–AVR–06/08 START SDA from Master A SDA from Master B SDA Line SCL Line ATmega16(L) Master A Loses Arbitration, SDA SDA A 177 ...
Page 178
... TWPS = Value of the prescaler bits in the TWI Status Register Note: Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, ATmega16(L) 178 SCL Slew-rate Spike ...
Page 179
... After the TWI has been addressed by own Slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition 2466R–AVR–06/08 ATmega16(L) 179 ...
Page 180
... The application writes the TWSTA bit to one when it desires to become a Master on the Two- wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START con- dition on the bus free. However, if the bus is not free, the TWI waits until a STOP condition ATmega16(L) 180 7 ...
Page 181
... Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. 2466R–AVR–06/ TWS7 TWS6 TWS5 TWS4 TWS3 ATmega16( – TWPS1 TWPS0 TWSR R R R/W R 181 ...
Page 182
... Slave address (or general call address if enabled) in the received serial address match is found, an interrupt request is generated. • Bits 7..1 – TWA: TWI (Slave) Address Register These seven bits constitute the Slave address of the TWI unit. ATmega16(L) 182 TWPS1 TWPS0 ...
Page 183
... TWCR, making sure that TWINT is written to one SLA TWINT set. Status code indicates SLA+W sent, ACK received ATmega16(L) 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWINT is written to one Data A STOP 6 ...
Page 184
... TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. ATmega16(L) 184 2466R–AVR–06/08 ...
Page 185
... MT_DATA_ACK) ERROR(); TWCR = (1<<TWINT)|(1<<TWEN)| (1<<TWSTO); ATmega16(L) Comments Send START condition Wait for TWINT Flag set. This indicates that the START condition has been transmitted Check value of TWI Status Register. Mask prescaler bits ...
Page 186
... MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 86. Data Transfer in Master Transmitter Mode SDA SCL ATmega16(L) 186 to Figure 93, circles are used to indicate that the TWINT Flag is set. The numbers in ...
Page 187
... TWINT TWEA TWSTA TWSTO Application Software Response To TWCR To/from TWDR STA STO TWINT Load SLA Load SLA Load SLA ATmega16(L) TWWC TWEN – TWIE Table 74). In order to enter MT mode, TWWC TWEN – TWIE TWWC TWEN – TWIE TWWC TWEN – TWIE ...
Page 188
... SLA+W has been transmitted; NOT ACK has been received $28 Data byte has been transmitted; ACK has been received $30 Data byte has been transmitted; NOT ACK has been received $38 Arbitration lost in SLA+W or data bytes ATmega16(L) 188 Load data byte TWDR action TWDR action or ...
Page 189
... MT S SLA W A $08 $ $38 A $68 $78 DATA From master to slave From slave to master 88). In order to enter a Master mode, a START condition must be transmitted. The ATmega16(L) DATA A P $28 R SLA S $ $30 Other master Other master continues continues $38 Other master ...
Page 190
... Table 75. Status Codes for Master Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware ATmega16(L) 190 Device 1 Device 2 Device 3 MASTER SLAVE RECEIVER TRANSMITTER TWINT ...
Page 191
... Other master A continues $68 $78 $B0 DATA From master to slave From slave to master n ATmega16(L) X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+R will be transmitted ACK or NOT ACK will be received X SLA+W will be transmitted Logic will switch to masTer Transmitter mode X Two-wire Serial Bus will be released and not addressed ...
Page 192
... Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. ATmega16(L) 192 90). All the status codes mentioned in this section assume that the prescaler bits are ...
Page 193
... Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 2466R–AVR–06/08 ATmega16(L) 193 ...
Page 194
... Previously addressed with general call; data has been received; NOT ACK has been returned $A0 A STOP condition or repeated START condition has been received while still addressed as Slave ATmega16(L) 194 Application Software Response To TWCR To/from TWDR STA STO TWINT No TWDR action or X ...
Page 195
... DATA From master to slave From slave to master 92). All the status codes mentioned in this section assume that the prescaler bits are Device 1 Device 2 SLAVE MASTER TRANSMITTER RECEIVER TWA6 TWA5 TWA4 Device’s Own Slave Address ATmega16(L) A DATA A DATA $60 $80 $80 $88 A $68 A DATA A ...
Page 196
... SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. ATmega16(L) 196 TWINT TWEA ...
Page 197
... No TWDR action TWDR action TWDR action ATmega16(L) TWEA Next Action Taken by TWI Hardware 0 Last data byte will be transmitted and NOT ACK should be received 1 Data byte will be transmitted and ACK should be re- ceived 0 Last data byte will be transmitted and NOT ACK should be received ...
Page 198
... Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware $F8 No relevant state information available; TWINT = “0” $00 Bus error due to an illegal START or STOP condition ATmega16(L) 198 S SLA R A $A8 A $B0 DATA From master to slave From slave to master ...
Page 199
... Figure 95. An Arbitration Example SDA SCL 2466R–AVR–06/08 Master Transmitter SLA+W A ADDRESS REPEATED START Transmitted from Master to Slave Device 1 Device 2 Device 3 MASTER SLAVE MASTER TRANSMITTER RECEIVER TRANSMITTER ATmega16(L) Master Receiver Rs SLA+R A DATA Transmitted from Slave to Master V CC ........ Device STOP R2 199 ...
Page 200
... Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. This is summarized in Figure 96. Possible Status Codes Caused by Arbitration START ATmega16(L) 200 Figure 96. Possible status values are given in circles. SLA Arbitration lost in SLA ...