DSPIC30F4013-30I/PT Microchip Technology, DSPIC30F4013-30I/PT Datasheet - Page 40

• Manufacturer Part Number: DSPIC30F4013-30I/PT
• Description: IC DSPIC MCU/DSP 48K 44TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4013-30I/PT

• Program Memory Type: FLASH
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 48KB (16K x 24)
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Data Rom Size: 1024 B
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC30F006 - MODULE SKT FOR DSPIC30F 44TQFPAC164305 - MODULE SKT FOR PM3 44TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F401330IPT

dsPIC30F3014/4013
4.2.3
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. It is important to realize that the address
boundaries check for addresses less than or greater
than the upper (for incrementing buffers) and lower (for
decrementing buffers) boundary addresses (not just
equal to). Address changes may, therefore, jump
beyond boundaries and still be adjusted correctly.
4.3
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.3.1
Bit-Reversed Addressing is enabled when:
1.
2.
3.
FIGURE 4-2:
DS70138G-page 40
Note:
b15 b14 b13 b12
b15 b14 b13 b12
BWM (W register selection) in the MODCON
register is any value other than ‘15’ (the stack
cannot
Addressing) and
the BREN bit is set in the XBREV register and
the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
Bit-Reversed Addressing
MODULO ADDRESSING
APPLICABILITY
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7+W2])
is used, Modulo Addressing correction is
performed but the contents of the register
remain unchanged.
BIT-REVERSED ADDRESSING
IMPLEMENTATION
be
accessed
b11 b10 b9 b8
BIT-REVERSED ADDRESS EXAMPLE
b11 b10 b9 b8
using
Bit-Reversed
b7 b6 b5 b4
b7 b6 b5 b1
Pivot Point
b3 b2 b1
b2 b3 b4
Sequential Address
Bit-Reversed Address
If the length of a bit-reversed buffer is M = 2
then the last ‘N’ bits of the data buffer start address
must be zeros.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing is only
executed for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data
writes. It does not function for any other addressing
mode or for byte sized data. Normal addresses are
generated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the Bit-Reversed Pointer.
Note:
Note:
XB = 0x0008 for a 16-word Bit-Reversed Buffer
0
0
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo Addressing and Bit-Reversed
Addressing
together. In the event that the user
attempts to do this, Bit-Reversed Address-
ing assumes priority when active for the X
WAGU, and X WAGU Modulo Addressing
is disabled. However, Modulo Addressing
continues to function in the X RAGU.
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
 2010 Microchip Technology Inc.
should
not
be
enabled
N
bytes,