PIC24FJ256GA106-I/PT Microchip Technology, PIC24FJ256GA106-I/PT Datasheet - Page 33
![IC PIC MCU FLASH 256K 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24FJ256GA106-I/PT
Manufacturer Part Number
PIC24FJ256GA106-I/PT
Description
IC PIC MCU FLASH 256K 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA008-IPT.pdf
(12 pages)
2.PIC24FJ128GA106-IPT.pdf
(14 pages)
3.PIC24FJ128GA106-IPT.pdf
(330 pages)
4.PIC24FJ128GA106-IPT.pdf
(52 pages)
5.PIC24FJ256GA106-IPT.pdf
(59 pages)
6.PIC24FJ128GB110-IPF.pdf
(292 pages)
Specifications of PIC24FJ256GA106-I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
53
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GA106-I/PT
Manufacturer:
AD
Quantity:
201
Company:
Part Number:
PIC24FJ256GA106-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 4-2:
2010 Microchip Technology Inc.
GWRP
ICS<1:0>
IESO
IOL1WAY
JTAGEN
OSCIOFCN
PLLDIV<2:0>
POSCMD<1:0>
PLL96MHz
Note 1:
2:
3:
Bit Field
(2)
Bits<23-16> should be programmed to a value of 0x00 to ensure that accidental program execution of any
of the Configuration Words would be interpreted as a NOP opcode.
The JTAGEN bit can be modified using only In-Circuit Serial Programming™ (ICSP™).
Irrespective of the WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Words
page, the Configuration Words page will be protected
PIC24FJXXXDA1/DA2/GB2 CONFIGURATION BITS DESCRIPTION (CONTINUED)
CW2<14:12> USB 96 MHz PLL Prescaler Select bits
Register
CW1<9:8>
CW2<1:0>
CW1<12>
CW2<15>
CW1<14>
CW2<11>
CW2<4>
CW2<5>
PIC24FJXXXDA1/DA2/GB2/GA3
(1)
General Segment Code Flash Write Protection bit
1 = Writes to program memory are allowed
0 = Writes to program memory are disabled
ICD Emulator Pin Placement Select bits
11 = Emulator functions are shared with PGEC1/PGED1
10 = Emulator functions are shared with PGEC2/PGED2
01 = Emulator functions are shared with PGEC3/PGED3
00 = Reserved; do not use
Internal External Switchover bit
1 = Two-Speed Start-up is enabled
0 = Two-Speed Start-up is disabled
IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (OSCCON<6>) can be set once, provided
0 = The IOLOCK is cleared as needed (provided an unlocking sequence
JTAG Enable bit
1 = JTAG port is enabled
0 = JTAG port is disabled
OSC2 Pin Function bit (except in XT and HS modes)
If POSCMD<1:0> = 11 or 00:
1 = OSCO/CLKO/RC15 functions as CLKO (F
0 = OSCO/CLKO/RC15 functions as port I/O (RC15)
If POSCMD<1:0> = 10 or 01:
OSCIOFCN has no effect on OSCO/CLKO/RC15
111 = Oscillator input divided by 12 (48 MHz input)
110 = Oscillator input divided by 8 (32 MHz input)
101 = Oscillator input divided by 6 (24 MHz input)
100 = Oscillator input divided by 5 (20 MHz input)
011 = Oscillator input divided by 4 (16 MHz input)
010 = Oscillator input divided by 3 (12 MHz input)
001 = Oscillator input divided by 2 (8 MHz input)
000 = Oscillator input used directly (4 MHz input)
Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = EC Oscillator mode is selected
1 = 96 MHz PLL is enabled automatically on start-up
0 = 96 MHz PLL is enabled by user in software (controlled with
USB 96 MHz PLL Start-up Enable bit
the unlock sequence has been completed. Once set, the Peripheral
Pin Select (PPS) registers cannot be written to a second time.
is executed)
the PLLEN bit in CLKDIV<5>)
Description
OSC
/2)
DS39970B-page 33