DSPIC33FJ128MC506A-I/PT Microchip Technology, DSPIC33FJ128MC506A-I/PT Datasheet - Page 85

IC DSPIC MCU/DSP 128K 64-TQFP

DSPIC33FJ128MC506A-I/PT

Manufacturer Part Number
DSPIC33FJ128MC506A-I/PT
Description
IC DSPIC MCU/DSP 128K 64-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC506A-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC33FJ128MC506A-I/PT
Manufacturer:
MICROCHIP
Quantity:
817
Part Number:
DSPIC33FJ128MC506A-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 6-3:
 2009 Microchip Technology Inc.
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
Reset Type
2:
3:
4:
5:
6:
T
T
Power-up Timer delay (if regulator is disabled). T
states, including waking from Sleep mode if the regulator is enabled.
T
T
oscillator clock to the system.
T
T
STARTUP
OST
RST
POR
LOCK
FSCM
= Internal state Reset time (20 s nominal).
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Power-on Reset delay (10 s nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time (20 s nominal).
= Fail-Safe Clock Monitor delay (100 s nominal).
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
Any Clock
= Conditional POR delay of 20 s nominal (if on-chip regulator is enabled) or 64 ms nominal
Clock Source
dsPIC33FJXXXMCX06A/X08A/X10A
T
T
T
T
POR
POR
POR
POR
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
Preliminary
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
STARTUP
RST
RST
RST
RST
+ T
+ T
+ T
+ T
RST
RST
RST
RST
is also applied to all returns from powered-down
System Clock
T
T
OST
OST
T
T
Delay
T
T
LOCK
LOCK
OST
+ T
OST
+ T
LOCK
LOCK
FSCM
T
T
T
T
T
T
Delay
FSCM
FSCM
FSCM
FSCM
FSCM
FSCM
DS70594B-page 85
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
3
3, 5, 6
3, 4, 6
3, 4, 5, 6
3
3
3
3
3
3
Notes

Related parts for DSPIC33FJ128MC506A-I/PT