DSPIC33FJ128GP310A-I/PT Microchip Technology, DSPIC33FJ128GP310A-I/PT Datasheet - Page 157

IC DSPIC MCU/DSP 128K 100-TQFP

DSPIC33FJ128GP310A-I/PT

Manufacturer Part Number
DSPIC33FJ128GP310A-I/PT
Description
IC DSPIC MCU/DSP 128K 100-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128GP310A-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
10.0
The dsPIC33FJXXXGPX06A/X08A/X10A devices pro-
vide the ability to manage power consumption by selec-
tively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and a
reduction in the number of circuits being clocked con-
stitutes
dsPIC33FJXXXGPX06A/X08A/X10A
manage power consumption in four different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
10.1
dsPIC33FJXXXGPX06A/X08A/X10A devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not
high-precision oscillators by simply changing the
NOSC bits (OSCCON<10:8>). The process of
changing a system clock during operation, as well as
limitations to the process, are discussed in more detail
in Section 9.0 “Oscillator Configuration”.
EXAMPLE 10-1:
 2009 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note 1: This data sheet summarizes the features
locked,
2: Some registers and associated bits
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
of
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section 9.
“Watchdog Timer and Power-Saving
Modes” (DS70196) in the “dsPIC33F/
PIC24H
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
lower
users
the dsPIC33FJXXXGPX06A/X08A/
PWRSAV INSTRUCTION SYNTAX
Family
can
dsPIC33FJXXXGPX06A/X08A/X10A
; Put the device into SLEEP mode
; Put the device into IDLE mode
consumed
choose
Reference
low-power
devices
Manual”,
power.
can
Preliminary
or
10.2
dsPIC33FJXXXGPX06A/X08A/X10A devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembly syntax of the PWRSAV
instruction is shown in Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
10.2.1
Sleep mode has these features:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
The device will wake-up from Sleep mode on any of
these events:
• Any interrupt source that is individually enabled.
• Any form of device Reset.
• A WDT time-out.
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports, or
peripherals that use an external clock input. Any
peripheral that requires the system clock source for
its operation is disabled in Sleep mode.
Note:
Instruction-Based Power-Saving
Modes
SLEEP MODE
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
DS70593B-page 157

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