DSPIC33FJ128GP310A-I/PT Microchip Technology, DSPIC33FJ128GP310A-I/PT Datasheet - Page 178

IC DSPIC MCU/DSP 128K 100-TQFP

DSPIC33FJ128GP310A-I/PT

Manufacturer Part Number
DSPIC33FJ128GP310A-I/PT
Description
IC DSPIC MCU/DSP 128K 100-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128GP310A-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
dsPIC33FJXXXGPX06A/X08A/X10A
15.1
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 15-1 lists the different bit settings for the Output
Compare modes. Figure 15-2 illustrates the output
compare operation for various modes. The user
TABLE 15-1:
FIGURE 15-2:
DS70593B-page 178
OCM<2:0>
000
001
010
011
100
101
110
111
Active-High One-Shot
Active-Low One-Shot
(OCM = 110 or 111)
Delayed One-Shot
Continuous Pulse
Output Compare Modes
(OCM = 001)
(OCM = 010)
(OCM = 011)
(OCM = 100)
(OCM = 101)
Module Disabled
Active-Low One-Shot
Active-High One-Shot
Toggle
Delayed One-Shot
Continuous Pulse
PWM without Fault Protection
PWM with Fault Protection
OUTPUT COMPARE MODES
Toggle
TMRy
PWM
OUTPUT COMPARE OPERATION
OCxRS
OCxR
Mode
Output Compare
Mode Enabled
Current output is maintained
Controlled by GPIO register
Preliminary
‘1’, if OCxR is non-zero
‘1’, if OCxR is non-zero
OCx Pin Initial State
‘0’, if OCxR is zero
‘0’, if OCxR is zero
Timer is Reset on
Period Match
0
1
0
0
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
Note:
See Section 13. “Output Compare”
(DS70209) in the “dsPIC33F/PIC24H
Family Reference Manual” for OCxR and
OCxRS register restrictions.
OCx rising edge
OCx falling edge
OCx rising and falling edge
OCx falling edge
OCx falling edge
No interrupt
OCFA falling edge for OC1 to OC4
OCx Interrupt Generation
 2009 Microchip Technology Inc.

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