DSPIC33FJ128GP310A-I/PT Microchip Technology, DSPIC33FJ128GP310A-I/PT Datasheet - Page 235

IC DSPIC MCU/DSP 128K 100-TQFP

DSPIC33FJ128GP310A-I/PT

Manufacturer Part Number
DSPIC33FJ128GP310A-I/PT
Description
IC DSPIC MCU/DSP 128K 100-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128GP310A-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
21.0
The
have up to 32 ADC input channels. These devices also
have up to 2 ADC modules (ADCx, where ‘x’ = 1 or 2),
each with its own set of Special Function Registers.
The AD12B bit (ADxCON1<10>) allows each of the
ADC modules to be configured by the user as either a
10-bit, 4-sample/hold ADC (default configuration) or a
12-bit, 1-sample/hold ADC.
21.1
The 10-bit ADC configuration has the following key
features:
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 32 analog input pins
• External voltage reference input pins
• Simultaneous sampling of up to four analog input
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
• Four result alignment options (signed/unsigned,
• Operation during CPU Sleep and Idle modes
The 12-bit ADC configuration supports all the above
features, except:
• In the 12-bit configuration, conversion speeds of
• There is only 1 sample/hold amplifier in the 12-bit
 2009 Microchip Technology Inc.
Note:
pins
fractional/integer)
up to 500 ksps are supported
configuration, so simultaneous sampling of
multiple channels is not supported.
Note 1: This data sheet summarizes the features
dsPIC33FJXXXGPX06A/X08A/X10A
2: Some registers and associated bits
10-BIT/12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
Key Features
The ADC module needs to be disabled
before modifying the AD12B bit.
of
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section
16.
(ADC)” (DS70183) in the “dsPIC33F/
PIC24H
which is available from the Microchip web
site (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
the dsPIC33FJXXXGPX06A/X08A/
“Analog-to-Digital
Family
dsPIC33FJXXXGPX06A/X08A/X10A
Reference
Converter
Manual”,
devices
Preliminary
Depending on the particular device pinout, the ADC
can have up to 32 analog input pins, designated AN0
through AN31. In addition, there are two analog input
pins for external voltage reference connections. These
voltage reference inputs may be shared with other
analog input pins. The actual number of analog input
pins and external voltage reference input configuration
will depend on the specific device. Refer to the device
data sheet for further details.
A block diagram of the ADC is shown in Figure 21-1.
21.2
The following configuration steps should be performed.
1.
2.
21.3
If more than one conversion result needs to be buffered
before triggering an interrupt, DMA data transfers can
be used. Both ADC1 and ADC2 can trigger a DMA data
transfer. If ADC1 or ADC2 is selected as the DMA IRQ
source, a DMA transfer occurs when the AD1IF or
AD2IF bit gets set as a result of an ADC1 or ADC2
sample conversion sequence.
The SMPI<3:0> bits (ADxCON2<5:2>) are used to
select how often the DMA RAM buffer pointer is
incremented.
The ADDMABM bit (ADxCON1<12>) determines how
the conversion results are filled in the DMA RAM buffer
area being used for ADC. If this bit is set, DMA buffers
are written in the order of conversion. The module will
provide an address to the DMA channel that is the
same as the address used for the non-DMA
stand-alone buffer. If the ADDMABM bit is cleared, then
DMA buffers are written in Scatter/Gather mode. The
module will provide a scatter/gather address to the
DMA channel, based on the index of the analog input
and the size of the DMA buffer.
Configure the ADC module:
a)
b)
c)
d)
e)
f)
g)
Configure ADC interrupt (if required):
a)
b)
ADC Initialization
Select port pins as analog inputs
(ADxPCFGH<15:0> or ADxPCFGL<15:0>).
Select voltage reference source to match
expected range on analog inputs
(ADxCON2<15:13>).
Select the analog conversion clock to match
desired data rate with processor clock
(ADxCON3<7:0>).
Determine how many S/H channels will be
used (ADxCON2<9:8> and
ADxPCFGH<15:0> or ADxPCFGL<15:0>).
Select the appropriate sample/conversion
sequence (ADxCON1<7:5> and
ADxCON3<12:8>).
Select how conversion results are presented
in the buffer (ADxCON1<9:8>).
Turn on ADC module (ADxCON1<15>).
Clear the ADxIF bit.
Select ADC interrupt priority.
ADC and DMA
DS70593B-page 235

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