DSPIC33FJ128GP310A-I/PT Microchip Technology, DSPIC33FJ128GP310A-I/PT Datasheet - Page 35

IC DSPIC MCU/DSP 128K 100-TQFP

DSPIC33FJ128GP310A-I/PT

Manufacturer Part Number
DSPIC33FJ128GP310A-I/PT
Description
IC DSPIC MCU/DSP 128K 100-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128GP310A-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
100-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
3.5
The dsPIC33FJXXXGPX06A/X08A/X10A ALU is 16
bits wide and is capable of addition, subtraction, bit
shifts and logic operations. Unless otherwise men-
tioned, arithmetic operations are 2’s complement in
nature. Depending on the operation, the ALU may
affect the values of the Carry (C), Zero (Z), Negative
(N), Overflow (OV) and Digit Carry (DC) Status bits in
the SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for subtrac-
tion operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.
The
incorporates hardware support for both multiplication
and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit-divisor
division.
3.5.1
Using the high-speed 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
1.
2.
3.
4.
5.
6.
7.
3.5.2
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
 2009 Microchip Technology Inc.
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
dsPIC33FJXXXGPX06A/X08A/X10A
Arithmetic Logic Unit (ALU)
MULTIPLIER
DIVIDER
dsPIC33FJXXXGPX06A/X08A/X10A
CPU
Preliminary
3.6
The
17-bit x 17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33FJXXXGPX06A/X08A/X10A is a sin-
gle-cycle, instruction flow architecture; therefore, concur-
rent operation of the DSP engine with MCU instruction
flow is not possible. However, some MCU ALU and DSP
engine resources may be used concurrently by the same
instruction (e.g., ED, EDAC).
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Control register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
Table 3-1 provides a summary of DSP instructions. A
block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
Instruction
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for AccA (SATA).
Automatic saturation on/off for AccB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection (ACCSAT).
DSP
DSP Engine
engine
DSP INSTRUCTIONS
SUMMARY
A = 0
A = (x – y)
A = A + (x – y)
A = A + (x * y)
A = A + x
No change in A
A = x * y
A = x
A = – x * y
A = A – x * y
Operation
Algebraic
consists
2
2
2
2
of
DS70593B-page 35
a
ACC Write
high-speed,
Back
Yes
Yes
Yes
Yes
No
No
No
No
No
No

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