DSPIC33FJ128GP310A-I/PT Microchip Technology, DSPIC33FJ128GP310A-I/PT Datasheet - Page 83
Manufacturer Part Number
IC DSPIC MCU/DSP 128K 100-TQFP
Specifications of DSPIC33FJ128GP310A-I/PT
Program Memory Type
Program Memory Size
128KB (128K x 8)
Package / Case
I²C, IrDA, LIN, SPI, UART/USART
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
-40°C ~ 85°C
Data Bus Width
Maximum Clock Frequency
Number Of Programmable I/os
Data Ram Size
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
The user can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
2009 Microchip Technology Inc.
; Set up NVMCON for block erase operation
; Init pointer to row to be ERASED
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 5-1):
Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
Write the starting address of the page to be
erased into the TBLPAG and W registers.
Write 55h to NVMKEY.
Write AAh to NVMKEY.
Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the
duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
TBLWTL W0, [W0]
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
ERASING A PROGRAM MEMORY PAGE
; Initialize NVMCON
; Initialize PM Page Boundary SFR
; Initialize in-page EA[15:0] pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 55 key
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
Write the program block to Flash memory:
Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
Write #0x55 to NVMKEY.
Write #0xAA to NVMKEY.
Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash
memory is done, the WR bit is cleared