PIC16LF877A-I/ML Microchip Technology, PIC16LF877A-I/ML Datasheet - Page 77
PIC16LF877A-I/ML
Manufacturer Part Number
PIC16LF877A-I/ML
Description
IC MCU FLASH 8KX14 A/D 44QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF877A-I/ML
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC16LF
No. Of I/o's
33
Eeprom Memory Size
256Byte
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9.3.3
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISC<4> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 9-2:
2003 Microchip Technology Inc.
cleared
SPI Master SSPM3:SSPM0 = 00xxb
ENABLING SPI I/O
MSb
PROCESSOR 1
Serial Input Buffer
SPI MASTER/SLAVE CONNECTION
Shift Register
(SSPBUF)
(SSPSR)
LSb
SDO
SCK
SDI
Serial Clock
9.3.4
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
SDO
SCK
SDI
SPI Slave SSPM3:SSPM0 = 010xb
TYPICAL CONNECTION
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SSPBUF)
(SSPSR)
PIC16F87XA
LSb
DS39582B-page 75
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