ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet - Page 136
ATMEGA1284P-PU
Manufacturer Part Number
ATMEGA1284P-PU
Description
MCU AVR 128K ISP FLASH 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
4.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-PU
Manufacturer:
LUCENT
Quantity:
32
- ATMEGA644PA-PU PDF datasheet
- ATMEGA644PA-PU PDF datasheet #2
- ATMEGA1284PR231-AU PDF datasheet #3
- ATMEGA1284P-MU PDF datasheet #4
- Current page: 136 of 581
- Download datasheet (27Mb)
15.11.3
8272A–AVR–01/10
TCCR1C – Timer/Counter1 Control Register C
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
• Bit 2:0 – CSn2:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
15-10
Table 15-6.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCRnA is written when operating in a PWM mode. When writing a logical one to the
FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform Generation unit.
The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the
FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the
COMnx1:0 bits that determine the effect of the forced compare.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Bit
(0x82)
Read/Write
Initial Value
CSn2
0
0
0
0
1
1
1
1
and
Figure
CSn1
0
0
1
1
0
0
1
1
Clock Select Bit Description
FOC1A
R/W
7
0
15-11.
CSn0
FOC1B
0
1
0
1
0
1
0
1
R/W
6
0
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
External clock source on Tn pin. Clock on falling edge.
External clock source on Tn pin. Clock on rising edge.
I/O
I/O
I/O
I/O
I/O
R
5
–
0
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
4
R
0
–
R
3
–
0
R
2
–
0
R
1
–
0
R
0
–
0
TCCR1C
Figure
136
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