ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet - Page 21
ATMEGA1284P-PU
Manufacturer Part Number
ATMEGA1284P-PU
Description
MCU AVR 128K ISP FLASH 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
4.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-PU
Manufacturer:
LUCENT
Quantity:
32
- ATMEGA644PA-PU PDF datasheet
- ATMEGA644PA-PU PDF datasheet #2
- ATMEGA1284PR231-AU PDF datasheet #3
- ATMEGA1284P-MU PDF datasheet #4
- Current page: 21 of 581
- Download datasheet (27Mb)
7.3.1
8272A–AVR–01/10
Data Memory Access Times
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and
t h e 1 0 2 4 / 2 0 4 8 / 4 0 9 6 b y t e s o f i n t e r n a l d a t a S R A M i n t h e
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P are all accessible through all these
addressing modes. The Register File is described in
13.
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 7-3.
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Address
clk
Data Memory Map for
ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
(1024/2048/4096/16384x 8)
RD
160 Ext I/O Reg.
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
Compute Address
T1
Memory Access Instruction
0x0000 - 0x001F
0x0100
0x04FF/0x08FF/0x10FF /0x40FF
0x0020 - 0x005F
0x0060 - 0x00FF
Address valid
CPU
T2
”General Purpose Register File” on page
cycles as described in
Next Instruction
T3
Figure
7-3.
21
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