ATMEGA1284P-PU Atmel, ATMEGA1284P-PU Datasheet - Page 91
ATMEGA1284P-PU
Manufacturer Part Number
ATMEGA1284P-PU
Description
MCU AVR 128K ISP FLASH 40-PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284PR231-AU.pdf
(380 pages)
4.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-PU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
4KB
Ram Memory Size
16KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA1284P-PU
Manufacturer:
LUCENT
Quantity:
32
- ATMEGA644PA-PU PDF datasheet
- ATMEGA644PA-PU PDF datasheet #2
- ATMEGA1284PR231-AU PDF datasheet #3
- ATMEGA1284P-MU PDF datasheet #4
- Current page: 91 of 581
- Download datasheet (27Mb)
8272A–AVR–01/10
Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0
Note:
164A/164PA/324A/324PA/644A/644PA/1284/1284P
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
PD3/INT1/TXD1/
PCINT27
TXEN1
0
TXEN1
1
TXEN1
TXD1
INT1 ENABLE
PCINT27 • PCIE3
1
INT1 INPUT
PCINT27 INPUT
–
PD2/INT0/RXD1/
PCINT26
PORTD2 • PUD
RXEN1
0
0
INT2 ENABLE
PCINT26 • PCIE3
1
INT0 INPUT
RXD1
PCINT26 INPUT
–
RXEN1
0
PD1/TXD0/
PCINT25
TXEN0
0
TXEN0
1
TXEN0
TXD0
PCINT25 • PCIE3
1
PCINT25 INPUT
–
(1)
PD0/RXD0/
PCINT27
RXEN1
PORTD0 • PUD
RXEN1
0
0
0
PCINT24 • PCIE3
1
RXD0
PCINT24 INPUT
–
91
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