DSPIC33FJ128GP708-I/PT Microchip Technology, DSPIC33FJ128GP708-I/PT Datasheet - Page 219

• Manufacturer Part Number: DSPIC33FJ128GP708-I/PT
• Description: IC DSPIC MCU/DSP 128K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 69
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.0
20.1
The dsPIC33FJXXXGPX06/X08/X10 Data Converter
Interface (DCI) module allows simple interfacing of
devices, such as audio coder/decoders (Codecs), ADC
and D/A converters. The following interfaces are sup-
ported:
• Framed Synchronous Serial Transfer (Single or
• Inter-IC Sound (I
• AC-Link Compliant mode
The DCI module provides the following general
features:
• Programmable word size up to 16 bits
• Supports up to 16 time slots, for a maximum
• Data buffering for up to 4 samples without CPU
20.2
There are four I/O pins associated with the module.
When enabled, the module controls the data direction
of each of the four pins.
20.2.1
The CSCK pin provides the serial clock for the DCI
module. The CSCK pin may be configured as an input
or output using the CSCKD control bit in the DCICON1
SFR. When configured as an output, the serial clock is
provided
When configured as an input, the serial clock must be
provided by an external device.
20.2.2
The Serial Data Output (CSDO) pin is configured as an
output only pin when the module is enabled. The
CSDO pin drives the serial bus whenever data is to be
transmitted. The CSDO pin is tri-stated, or driven to ‘0’,
during CSCK periods when data is not transmitted
depending on the state of the CSDOM control bit. This
© 2009 Microchip Technology Inc.
Note:
Multi-Channel)
frame size of 256 bits
overhead
DATA CONVERTER
INTERFACE (DCI) MODULE
Module Introduction
Module I/O Pins
by
This data sheet summarizes the features
of the dsPIC33FJXXXGPX06/X08/X10
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 20. “Data
Converter Interface (DCI)” (DS70288) in
the “dsPIC33F Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
CSCK PIN
CSDO PIN
the
2
S) Interface
dsPIC33FJXXXGPX06/X08/X10.
dsPIC33FJXXXGPX06/X08/X10
allows other devices to place data on the serial bus
during transmission periods not used by the DCI
module.
20.2.3
The Serial Data Input (CSDI) pin is configured as an
input only pin when the module is enabled.
20.2.3.1
The Codec Frame Synchronization (COFS) pin is used
to synchronize data transfers that occur on the CSDO
and CSDI pins. The COFS pin may be configured as an
input or an output. The data direction for the COFS pin
is determined by the COFSD control bit in the
DCICON1 register.
The DCI module accesses the shadow registers while
the CPU is in the process of accessing the memory
mapped buffer registers.
20.2.4
Data values are always stored left justified in the
buffers since most Codec data is represented as a
signed 2’s complement fractional number. If the
received word length is less than 16 bits, the unused
Least Significant bits in the Receive Buffer registers are
set to ‘0’ by the module. If the transmitted word length
is less than 16 bits, the unused LSbs in the Transmit
Buffer register are ignored by the module. The word
length setup is described in subsequent sections of this
document.
20.2.5
The DCI module has a 16-bit shift register for shifting
serial data in and out of the module. Data is shifted
in/out of the shift register, MSb first, since audio PCM
data is transmitted in signed 2’s complement format.
20.2.6
The DCI module contains a buffer control unit for
transferring data between the shadow buffer memory
and the Serial Shift register. The buffer control unit is a
simple 2-bit address counter that points to word loca-
tions in the shadow buffer memory. For the receive
memory space (high address portion of DCI buffer
memory), the address counter is concatenated with a
‘0’ in the MSb location to form a 3-bit address. For the
transmit memory space (high portion of DCI buffer
memory), the address counter is concatenated with a
‘1’ in the MSb location.
Note:
CSDI PIN
BUFFER DATA ALIGNMENT
TRANSMIT/RECEIVE SHIFT
REGISTER
DCI BUFFER CONTROL
The DCI buffer control unit always
accesses the same relative location in the
transmit and receive buffers, so only one
address counter is provided.
COFS Pin
DS70286C-page 217