DSPIC33FJ128GP708-I/PT Microchip Technology, DSPIC33FJ128GP708-I/PT Datasheet - Page 243

• Manufacturer Part Number: DSPIC33FJ128GP708-I/PT
• Description: IC DSPIC MCU/DSP 128K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 69
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.2
All of the dsPIC33FJXXXGPX06/X08/X10 devices
power their core digital logic at a nominal 2.5V. This
may create an issue for designs that are required to
operate at a higher typical voltage, such as 3.3V. To
simplify
dsPIC33FJXXXGPX06/X08/X10 family incorporate an
on-chip regulator that allows the device to run its core
logic from V
The regulator provides power to the core from the
other V
low-ESR (less than 5 ohms) capacitor (such as
tantalum
V
maintain
recommended value for the filter capacitor is
provided in Table 25-13 of Section 25.0 “Electrical
Characteristics”.
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 22-1:
© 2009 Microchip Technology Inc.
CAP
Note 1:
Note:
/V
DDCORE
2:
DD
On-Chip Voltage Regulator
C
,
system
EFC
STARTUP
or
the
it takes approximately 20 s for the on-chip
It is important for the low-ESR capacitor to
be placed as close as possible to the
V
DD
These are typical operating voltages. Refer to
TABLE 25-13: “Internal Voltage Regulator
Specifications” located in Section 25.1 “DC
Characteristics” for the full operating ranges
of V
It is important for the low-ESR capacitor to be
placed as close as possible to the
V
CAP
pins. The regulator requires that a
CAP
.
3.3V
DD
ceramic)
/V
/V
pin (Figure 22-1). This helps to
stability
and V
DDCORE
DDCORE
design,
is applied every time the device
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
V
V
V
CAP
DD
CAP
SS
dsPIC33F
STARTUP
pin.
/V
of
pin.
be
/V
DDCORE
DDCORE
all
the
connected
, code execution is
devices
.
dsPIC33FJXXXGPX06/X08/X10
regulator.
(1)
to
in
The
the
the
22.3
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit that monitors the
regulated voltage V
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines or voltage sags due to
excessive current draw when a large inductive load is
turned on).
A BOR will generate a Reset pulse which will reset the
device. The BOR will select the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>). Furthermore, if an oscillator mode is
selected, the BOR will activate the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock will be held
until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) will be
applied before the internal Reset is released. If
TPWRT = 0 and a crystal oscillator is being used, then
a nominal delay of TFSCM = 100 is applied. The total
delay in this case is TFSCM.
The BOR Status bit (RCON<1>) will be set to indicate
that a BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and will reset the
device should VDD fall below the BOR threshold
voltage.
BOR: Brown-Out Reset
CAP
/V
DDCORE
. The main purpose of
DS70286C-page 241