DSPIC33FJ128GP708-I/PT Microchip Technology, DSPIC33FJ128GP708-I/PT Datasheet - Page 312

• Manufacturer Part Number: DSPIC33FJ128GP708-I/PT
• Description: IC DSPIC MCU/DSP 128K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 80-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 69
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJXXXGPX06/X08/X10
Revision C (March 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
• Changed all instances of V
The other changes are referenced by their respective
section in the following table.
TABLE A-2:
DS70286C-page 310
“High-Performance, 16-Bit Digital
Signal Controllers”
Section 1.0 “Device Overview”
Section 2.0 “Guidelines for Getting
Started with 16-Bit Digital Signal
Controllers”
Section 4.0 “Memory Organization”
Section 5.0 “Flash Program Memory” Updated Section 5.3 “Programming Operations” with programming
Section 9.0 “Oscillator Configuration” Added Note 2 to the Oscillator System Diagram (see Figure 9-1).
Section 10.0 “Power-Saving
Features”
Section 11.0 “I/O Ports”
Section 16.0 “Serial Peripheral
Interface (SPI)”
Section 18.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
OSCO to OSC2
V
DDCORE
/V
Section Name
CAP
to V
MAJOR SECTION UPDATES
CAP
/V
DDCORE
DDCORE
and
Updated all pin diagrams to denote the pin voltage tolerance (see “Pin
Diagrams”).
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which
references pin connections to V
Updated AV
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Digital Signal Controllers.
Add Accumulator A and B SFRs (ACCAL, ACCAH, ACCAU, ACCBL,
ACCBH and ACCBU) and updated the Reset value for CORCON in the
CPU Core Register Map (see Table 4-1).
Updated Reset values for IPC3, IPC4, IPC11 and IPC13-IPC15 in the
Interrupt Controller Register Map (see Table 4-5).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 4-32).
time formula.
Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock
Divisor (CLKDIV) Register (see Register 9-2).
Added a paragraph regarding FRC accuracy at the end of Section 9.1.1
“System Clock sources”.
Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see
Register 9-4).
Added the following registers:
• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)
• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)
• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)
Added reference to pin diagrams for I/O pin availability and functionality
(see Section 11.2 “Open-Drain Configuration”).
Added Note 2 to the SPIxCON1 register (see Register 16-2).
Updated the UTXINV bit settings in the UxSTA register (see
Register 18-2).
DD
in the PINOUT I/O Descriptions (see Table 1-1).
Update Description
SS
.
© 2009 Microchip Technology Inc.