DSPIC33FJ128GP708-I/PT Microchip Technology, DSPIC33FJ128GP708-I/PT Datasheet - Page 18

no-image

DSPIC33FJ128GP708-I/PT

Manufacturer Part Number
DSPIC33FJ128GP708-I/PT
Description
IC DSPIC MCU/DSP 128K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP708-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
80-TFQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
69
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1001 - DSPIC33 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1DV164033 - KIT START EXPLORER 16 MPLAB ICD2MA330012 - MODULE DSPIC33 100P TO 84QFPMA330011 - MODULE DSPIC33 100P TO 100QFPDM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
dsPIC33F
5.0
The dsPIC33F has four processor exceptions (traps)
and up to 67 sources of interrupts, which must be
arbitrated based on a priority scheme.
The processor core is responsible for reading the
Interrupt Vector Table (IVT) and transferring the
address contained in the interrupt vector to the
program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004) for ease of debugging.
The interrupt controller hardware pre-processes the
interrupts before they are presented to the CPU.
The interrupts and traps are enabled, prioritized and
controlled using centralized Special Function Registers.
TABLE 5-1:
DS70155C-page 16
Number
Vector
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
11
8
9
EXCEPTION PROCESSING
INTERRUPT VECTORS
IVT Address
0x00001A
0x00001C
0x00001E
0x00002A
0x00002C
0x00002E
0x00003A
0x00003C
0x00003E
0x00004A
0x00004C
0x00004E
0x000014
0x000016
0x000018
0x000020
0x000022
0x000024
0x000026
0x000028
0x000030
0x000032
0x000034
0x000036
0x000038
0x000042
0x000044
0x000046
0x000048
0x000050
0x000052
0x000040
AIVT Address
0x00012C
0x00013C
0x00014C
0x00011A
0x00011C
0x00011E
0x00012A
0x00012E
0x00013A
0x00013E
0x00014A
0x00014E
0x000114
0x000116
0x000118
0x000120
0x000122
0x000124
0x000126
0x000128
0x000130
0x000132
0x000134
0x000136
0x000138
0x000142
0x000144
0x000146
0x000148
0x000150
0x000152
0x000140
Preliminary
INT0 – External Interrupt 0
IC1 – Input Compare 1
OC1 – Output Compare 1
T1 – Timer1
DMA0 – DMA Channel 0
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
T3 – Timer3
SPI1E – SPI1 Error
SPI1D – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC1 – A/D Converter 1
DMA1 – DMA Channel 1
Reserved
I2C1D – I2C1 Transfer Done
I2C1E – I2C1 Bus Collision Error
Reserved
Change Notification Interrupt
INT1 – External Interrupt 1
ADC2 – A/D Converter 2
IC7 – Input Capture 7
IC8 – Input Capture 8
DMA2 – DMA Channel 2
OC3 – Output Compare 3
OC4 – Output Compare 4
T4 – Timer4
T5 – Timer5
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
features like edge or level triggered interrupts, interrupt-
Each individual interrupt source has its own vector
address and can be individually enabled and prioritized
in user software. Each interrupt source also has its own
status flag. This independent control and monitoring of
the interrupt eliminates the need to poll various status
flags to determine the interrupt source
Table 5-1 contains information about the interrupt
vector.
Certain interrupts have specialized control bits for
on-change, etc. Control of these features remains within
the peripheral module, which generates the interrupt.
The special DISI instruction can be used to disable
the processing of interrupts of priorities 6 and lower for
a certain number of instruction cycles, during which
the DISI bit remains set.
Interrupt Source
© 2005 Microchip Technology Inc.

Related parts for DSPIC33FJ128GP708-I/PT