PIC18LF452-I/P Microchip Technology, PIC18LF452-I/P Datasheet - Page 212
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PIC18LF452-I/P
Manufacturer Part Number
PIC18LF452-I/P
Description
IC MCU FLASH 16KX16 A/D 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18LF452-I/P
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
34
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
MSSP, SPI, I2C, PSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
1 x 16 bit
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF452-I/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18LF452-I/PT
Manufacturer:
XILINX
Quantity:
349
Company:
Part Number:
PIC18LF452-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18LF452-I/PT
Manufacturer:
MICROCH
Quantity:
20 000
PIC18FXX2
19.4.2
The entire Data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of Data EEPROM.
WRTD inhibits external writes to Data EEPROM. The
CPU can continue to read and write Data EEPROM
regardless of the protection bit settings.
19.4.3
The configuration registers can be write protected. The
WRTC bit controls protection of the configuration regis-
ters. In User mode, the WRTC bit is readable only. WRTC
can only be written via ICSP or an external programmer.
19.5
Eight memory locations (200000h - 200007h) are des-
ignated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD and TBLWT instructions, or during
program/verify. The ID locations can be read when the
device is code protected.
The sequence for programming the ID locations is sim-
ilar to programming the FLASH memory (see
Section 5.5.1).
19.6
PIC18FXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
19.7
When the DEBUG bit in configuration register
CONFIG4L is programmed to a '0', the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB
IDE. When the microcontroller has this feature
enabled, some of the resources are not available for
general use. Table 19-4 shows which features are
consumed by the background debugger.
TABLE 19-4:
DS39564C-page 210
Stack
Program Memory
Data Memory
I/O pins
ID Locations
In-Circuit Debugger
In-Circuit Serial Programming
DATA EEPROM
CODE PROTECTION
CONFIGURATION REGISTER
PROTECTION
DEBUGGER RESOURCES
RB6, RB7
512 bytes
10 bytes
2 levels
®
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/V
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
19.8
The LVP bit configuration register CONFIG4L enables
low voltage ICSP programming. This mode allows the
microcontroller to be programmed via ICSP using a
V
means that V
but can instead be left at the normal operating voltage.
In this mode, the RB5/PGM pin is dedicated to the pro-
gramming function and ceases to be a general purpose
I/O pin. During programming, V
MCLR/V
be applied to the RB5/PGM, provided the LVP bit is set.
The LVP bit defaults to a (‘1’) from the factory.
If Low Voltage Programming mode is not used, the LVP
bit can be programmed to a '0' and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
grammed when programming is entered with V
MCLR/V
It should be noted that once the LVP bit is programmed
to 0, only the High Voltage Programming mode is avail-
able and only High Voltage Programming mode can be
used to program the device.
When using low voltage ICSP, the part must be sup-
plied 4.5V to 5.5V, if a bulk erase will be executed. This
includes reprogramming of the code protect bits from
an on-state to off-state. For all other cases of low volt-
age ICSP, the part may be programmed at the normal
operating voltage. This means unique user IDs, or user
code can be reprogrammed or added.
DD
Note 1: The High Voltage Programming mode is
source in the operating voltage range. This only
PP
PP
Low Voltage ICSP Programming
2: While in low voltage ICSP mode, the RB5
3: When using low voltage ICSP program-
.
pin. To enter Programming mode, V
always available, regardless of the state
of the LVP bit, by applying V
MCLR pin.
pin can no longer be used as a general
purpose I/O pin, and should be held low
during
against inadvertent ICSP mode entry.
ming (LVP), the pull-up on RB5 becomes
disabled. If TRISB bit 5 is cleared,
thereby setting RB5 as an output, LATB
bit 5 must also be cleared for proper
operation.
PP
does not have to be brought to V
normal
© 2006 Microchip Technology Inc.
operation
DD
is applied to the
PP
, V
to
IHH
DD
DD
protect
, GND,
to the
IHH
must
IHH
on
,