PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet - Page 2

• Manufacturer Part Number: PIC24FJ256GB110-I/PF
• Description: IC PIC MCU FLASH 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 83
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

regulator. The specifications for core voltage and capac-
PIC24FJXXXGA1/GB1
2.1
All devices in the PIC24FJXXXGA1/GB1 families are
dual voltage supply designs: one supply for the core
and peripherals and another for the I/O pins. A regula-
tor is provided on-chip to alleviate the need for two
external voltage supplies.
All PIC24FJXXXGA1/GB1 devices power their core
digital logic at a nominal 2.5V. To simplify system
design, all devices in the PIC24FJXXXGA1/GB1 fami-
lies incorporate an on-chip regulator that allows the
device to run its core logic from V
The regulator provides power to the core from the other
V
be connected to the V
Figure 2-2). This helps to maintain the stability of the
itance are listed in Section 7.0 “AC/DC Characteristics
and Timing Requirements”.
2.2
The Flash program memory on PIC24FJXXXGA1/GB1
devices has a specific write/erase requirement that
must be adhered to for proper device operation. The
rule is that any given word in memory must not be writ-
ten more than twice before erasing the page in which it
is located. Thus, the easiest way to conform to this rule
is to write all the data in a programming block within
one write cycle. The programming methods specified in
this specification comply with this requirement.
2.3
The pin diagrams for the PIC24FJXXXGA1/GB1 fami-
lies are shown in the following figures. The pins that are
required for programming are listed in Table 2-1 and
are shown in bold letters in the figures. Refer to the
appropriate device data sheet for complete pin
descriptions.
2.3.1
All of the devices in the PIC24FJXXXGA1/GB1 families
have three separate pairs of programming pins,
labelled as PGEC1/PGED1, PGEC2/PGED2, and
PGEC3/PGED3. Any one of these pin pairs may be
used for device programming by either ICSP or
Enhanced ICSP. Unlike voltage supply and ground
pins, it is not necessary to connect all three pin pairs to
program the device. However, the programming
method must use both pins of the same pair.
DS39907A-page 2
DD
Note:
pins. A low-ESR capacitor (such as tantalum) must
Power Requirements
Program Memory Write/Erase
Requirements
Pin Diagrams
Writing to a location multiple times without
erasing is not recommended.
PGCx AND PGDx PIN PAIRS
DDCORE
DD
pin (Table 2-1 and
.
FIGURE 2-2:
Regulator Enabled (ENVREG tied to V
Regulator Disabled (ENVREG tied to ground):
Regulator Disabled (V
Note 1: These are typical operating voltages. Refer
(10
2.5V
2.5V
C
μ
EFC
to Section 7.0 “AC/DC Characteristics and
Timing Requirements” for the full operating
ranges of V
(1)
(1)
F typ)
3.3V
3.3V
(1)
DD
CONNECTIONS FOR THE
ON-CHIP REGULATOR
© 2007 Microchip Technology Inc.
DD
and V
V
ENVREG
V
V
PIC24FJXXXGA1/GB1
V
ENVREG
V
V
PIC24FJXXXGA1/GB1
V
ENVREG
V
V
PIC24FJXXXGA1/GB1
tied to V
DD
DDCORE
SS
DD
DDCORE
SS
DD
DDCORE
SS
DDCORE
/V
/V
DDCORE
/V
CAP
CAP
CAP
.
DD
):
):