PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet - Page 29

• Manufacturer Part Number: PIC24FJ256GB110-I/PF
• Description: IC PIC MCU FLASH 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 83
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6
4.6.1
The PIC24FJXXXGA1/GB1 families have Configura-
tion bits stored in the last three locations of imple-
mented program memory (see Table 2-2 for locations).
These bits can be set or cleared to select various
device configurations. There are three types of Config-
uration bits: system operation bits, code-protect bits
and unit ID bits. The system operation bits determine
the power-on settings for system level components,
such
code-protect bits prevent program memory from being
read and written.
TABLE 4-2:
© 2007 Microchip Technology Inc.
DEBUG
DISUVREG
FCKSM<1:0>
FNOSC<2:0>
FWDTEN
FWPSA
GCP
GWRP
Note 1:
Bit Field
as oscillator
2:
Configuration Bits Programming
Available on PIC24FJXXXGB1XX devices only.
Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’.
OVERVIEW
(1)
PIC24FJXXXGA1/GB1 CONFIGURATION BITS DESCRIPTION
and Watchdog
CW2<10:8>
CW2<7:6>
CW1<13>
CW1<12>
CW1<11>
Register
CW2<3>
CW1<7>
CW1<4>
Background Debug Enable bit
1 = Device will reset in User mode
0 = Device will reset in Debug mode
Internal USB 3.3v Regulator Disable bit
1 = Regulator is disabled
0 = Regulator is enabled
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRCDIV) oscillator with postscaler
110 = Reserved
101 = Low-Power RC (LPRC) oscillator
100 = Secondary (SOSC) oscillator
011 = Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL
010 = Primary (XT, HS, EC) oscillator
001 = Internal Fast RC (FRCPLL) oscillator with postscaler and PLL
000 = Fast RC (FRC) oscillator
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled;
0 = Watchdog Timer enabled/disabled by user software (LPRC can be
Watchdog Timer Postscaler bit
1 = 1:128
0 = 1:32
General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = User program memory is code-protected
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
Timer.
clearing the SWDTEN bit in the RCON register will have no effect)
disabled by clearing the SWDTEN bit in the RCON register)
The
PIC24FJXXXGA1/GB1
The descriptions for the Configuration bits in the Flash
Configuration Words are shown in Table 4-2.
Note:
Description
Although not implemented with a specific
function, some Configuration bit positions
have default states that must always be
maintained to ensure device functionality,
regardless of the settings of other Config-
uration bits. Refer to Table 3-7 for a list of
these bit positions and their default states.
DS39907A-page 29