DSPIC33FJ128GP710A-I/PF Microchip Technology, DSPIC33FJ128GP710A-I/PF Datasheet - Page 91

• Manufacturer Part Number: DSPIC33FJ128GP710A-I/PF
• Description: IC DSPIC MCU/DSP 128K 100-TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128GP710A-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 16 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.0
The
controller reduces the numerous peripheral interrupt
request signals to a single interrupt request signal to
the dsPIC33FJXXXGPX06A/X08A/X10A CPU. It has
the following features:
• Up to eight processor exceptions and software
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
• Fixed interrupt entry and return latencies
7.1
The Interrupt Vector Table is shown in Figure 7-1. The
IVT resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight non-maskable trap vectors plus up to 118 sources
of interrupt. In general, each interrupt source has its
own vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority; this priority is linked to their position in the
vector table. All other things being equal, lower
addresses have a higher natural priority. For example,
the interrupt associated with vector 0 will take priority
over interrupts at any other vector address.
dsPIC33FJXXXGPX06A/X08A/X10A devices imple-
ment up to 67 unique interrupts and five non-maskable
traps. These are summarized in Table 7-1 and
Table 7-2.
 2009 Microchip Technology Inc.
traps
source
support
Note 1: This data sheet summarizes the features
dsPIC33FJXXXGPX06A/X08A/X10A
2: Some registers and associated bits
INTERRUPT CONTROLLER
Interrupt Vector Table
of
X10A family of devices. However, it is not
intended to be a comprehensive refer-
ence source. To complement the informa-
tion in this data sheet, refer to Section 6.
“Interrupts”
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
the dsPIC33FJXXXGPX06A/X08A/
dsPIC33FJXXXGPX06A/X08A/X10A
(DS70184)
in
interrupt
the
Preliminary
7.1.1
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports debugging by providing a means to
switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
7.2
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The
clears its registers in response to a Reset, which forces
the PC to zero. The digital signal controller then begins
program execution at location 0x000000. The user
programs a GOTO instruction at the Reset address
which redirects program execution to the appropriate
start-up routine.
Note:
is
dsPIC33FJXXXGPX06A/X08A/X10A
Reset Sequence
provided
ALTERNATE VECTOR TABLE
Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
by
the
ALTIVT
DS70593B-page 91
control
device
bit