AT89C51ED2-RDTUM Atmel, AT89C51ED2-RDTUM Datasheet - Page 69

IC 8051 MCU FLASH 64K 64VQFP

AT89C51ED2-RDTUM

Manufacturer Part Number
AT89C51ED2-RDTUM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ED2-RDTUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Cpu Family
AT89
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
2KB
# I/os (max)
50
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

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16.3.5
16.3.5.1
4235K–8051–05/08
Registers
Serial Peripheral Control Register (SPCON)
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been
completed. SPIF bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent
with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt
requests. When SSDIS is set, no MODF interrupt request is generated.
Figure 16-7 gives a logical view of the above statements.
Figure 16-7. SPI Interrupt Requests Generation
There are three registers in the Module that provide control, status and data storage functions. These registers are
describes in the following paragraphs.
Table 16-3 describes this register and explains the use of each bit
Table 16-3.
SPCON - Serial Peripheral Control Register (0C3H)
• The Serial Peripheral Control Register does the following:
• Selects one of the Master clock rates
• Configure the SPI Module as Master or Slave
• Selects serial clock polarity and phase
• Enables the SPI Module
• Frees the SS pin for a general-purpose
Bit Number
SPR2
7
7
6
5
SPIF
MODF
SSDIS
SPCON Register
SPEN
6
Bit Mnemonic
SSDIS
SPEN
SPR2
SSDIS
5
SPI Transmitter
CPU Interrupt Request
SPI Receiver/error
CPU Interrupt Request
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit
has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request
is generated
MSTR
4
.
CPOL
3
CPU Interrupt Request
AT89C51RD2/ED2
SPI
CPHA
2
SPR1
1
SPR0
0
69

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