AT89C51ED2-RDTUM Atmel, AT89C51ED2-RDTUM Datasheet - Page 95

IC 8051 MCU FLASH 64K 64VQFP

AT89C51ED2-RDTUM

Manufacturer Part Number
AT89C51ED2-RDTUM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ED2-RDTUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Cpu Family
AT89
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
2KB
# I/os (max)
50
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

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24.3.3
24.3.4
4235K–8051–05/08
Default Values
Software Registers
Table 24-2.
Note:
These security bits protect the code access through the parallel programming interface. They
are set by default to level 4. The code access through the ISP is still possible and is controlled
by the "software security bits" which are stored in the extra Flash memory accessed by the ISP
firmware.
To load a new application with the parallel programmer, a chip erase must first be done. This will
set the HSB in its inactive state and will erase the Flash memory. The part reference can always
be read using Flash parallel programming modes.
The default value of the HSB provides parts ready to be programmed with ISP:
Several registers are used in factory and by parallel programmers. These values are used by
Atmel ISP.
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also
called "XAF" or eXtra Array Flash. They are accessed in the following ways:
Several software registers are described in Table 24-3.
Table 24-3.
• BLJB: Programmed force ISP operation.
• X2: Unprogrammed to force X1 mode (Standard Mode).
• XRAM: Unprogrammed to valid XRAM
• LB2-0: Security level four to protect the code from a parallel access with maximum security.
• Commands issued by the parallel memory programmer.
• Commands issued by the ISP software.
• Calls of API issued by the application software.
Security
Mnemonic
Level
SBV
1
2
3
4
Program Lock Bits
U: Unprogrammed or "one" level.
P: Programmed or "zero" level.
X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.
LB0
U
P
X
X
Definition
Software Boot Vector
Program Lock Bits
Default Values
LB1
U
U
P
X
LB2
U
U
U
P
Protection Description
No program lock features enabled.
MOVC instruction executed from external program memory is disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further parallel programming of the on chip code memory is disabled.
ISP and software programming with API are still allowed.
Same as 2, also verify code memory through parallel programming interface is
disabled.
Same as 3, also external execution is disabled (Default).
Default value
FCh
AT89C51RD2/ED2
Description
95

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