AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 355

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

Figure 24-8. Transmitter Block Diagram
24.7.3
32015G–AVR32–09/09
Transmitter Clock
RX_FRAME_SYNC
Receiver Operations
TX_FRAME_SYNC
TFMR.DATLEN
TCMR.STTDLY
TFMR.FSDEN
Selector
Start
A received frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured setting the Receive Clock Mode Register (RCMR).
“24.7.4” on page 356.
The frame synchronization is configured setting the Receive Frame Mode Register (RFMR).
Section “24.7.5” on page 358.
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the RCMR. The data is transferred from the shift register depending on the data for-
mat selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the sta-
tus flag RXRDY is set in SR and the data can be read in the receiver holding register. If another
transfer occurs before read of the RHR register, the status flag OVERUN is set in SR and the
receiver shift register is transferred in the RHR register.
TFMR.MSBF
THR
Transmit Shift Register
TFMR.DATDEF
0
1
TSHR
0
1
TFMR.FSLEN
TCMR.STTDLY
TFMR.DATNB
TFMR.FSDEN
CR.TXEN
CR.TXDIS
SR.TXEN
AT32AP7001
TX_DATA
See Section
See
355