DSPIC30F6012A-30I/PT Microchip Technology, DSPIC30F6012A-30I/PT Datasheet - Page 45

• Manufacturer Part Number: DSPIC30F6012A-30I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012A30IP

11.8
The procedure for writing code memory is similar to the
procedure for clearing the Configuration registers,
except that 32 instruction words are programmed at a
time. To facilitate this operation, working registers
W0:W5 are used as temporary holding registers for the
data to be programmed.
Table 11-8
including the serial pattern with the ICSP command
code, which must be transmitted Least Significant bit
first using the PGC and PGD pins (see
Step 1, the Reset vector is exited. In Step 2, the
NVMCON register is initialized for single-panel
programming of code memory. In Step 3, the 24-bit
starting destination address for programming is loaded
into the TBLPAG register and W7 register. The upper
byte of the starting destination address is stored to
TBLPAG, while the lower 16 bits of the destination
address are stored to W7.
To minimize the programming time, the same packed
instruction format that the programming executive uses
is utilized
instruction words are stored to working registers
W0:W5 using the MOV instruction and the read pointer
W6 is initialized. The contents of W0:W5 holding the
packed instruction word data is shown in
TABLE 11-8:
© 2010 Microchip Technology Inc.
Step 1: Exit the Reset vector.
0000
0000
0000
Step 2: Set the NVMCON to program 32 instruction words.
0000
0000
Step 3: Initialize the write pointer (W7) for TBLWT instruction.
0000
0000
0000
Step 4: Initialize the read pointer (W6) and load W0:W5 with the next 4 instruction words to program.
0000
0000
0000
0000
0000
0000
Command
(Binary)
Writing Code Memory
shows the ICSP programming details,
(Figure
040100
040100
000000
24001A
883B0A
200xx0
880190
2xxxx7
2xxxx0
2xxxx1
2xxxx2
2xxxx3
2xxxx4
2xxxx5
(Hexadecimal)
SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY
8-2). In Step 4, four packed
Data
GOTO 0x100
GOTO 0x100
NOP
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Figure
#0x4001, W10
W10, NVMCON
#<DestinationAddress23:16>, W0
W0, TBLPAG
#<DestinationAddress15:0>, W7
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
Figure
11-2). In
11-4.
In Step 5, eight TBLWT instructions are used to copy the
data from W0:W5 to the write latches of code memory.
Since code memory is programmed 32 instruction
words at a time, Steps 4 and 5 are repeated eight times
to load all the write latches (Step 6).
After the write latches are loaded, programming is
initiated by writing to the NVMKEY and NVMCON
registers in Steps 7 and 8. In Step 9, the internal PC is
reset to 0x100. This is a precautionary measure to
prevent the PC from incrementing into unimplemented
memory when large devices are being programmed.
Lastly, in Step 10, Steps 2-9 are repeated until all of
code memory is programmed.
FIGURE 11-5:
W0
W1
W2
W3
W4
W5
Description
15
MSB1
MSB3
PACKED INSTRUCTION
WORDS IN W0:W5
lsw0
lsw1
lsw2
lsw3
8
7
DS70102K-page 45
MSB0
MSB2
0