DSPIC30F6012A-30I/PT Microchip Technology, DSPIC30F6012A-30I/PT Datasheet - Page 8

• Manufacturer Part Number: DSPIC30F6012A-30I/PT
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 144KB (48K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 8 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012A30IP

5.5.3
Once code memory is programmed, the contents of
memory can be verified to ensure that programming
was successful. Verification requires code memory to
be read back and compared against the copy held in
the programmer’s buffer.
The READP command can be used to read back all the
programmed code memory.
Alternatively, you can have the programmer perform
the verification once the entire device is programmed
using a checksum computation, as described in
Section 6.8 “Checksum
5.6
5.6.1
The panel architecture for the data EEPROM memory
array consists of 128 rows of sixteen 16-bit data words.
Each panel stores 2K words. All devices have either
one or no memory panels. Devices with data EEPROM
provide either 512 words, 1024 words or 2048 words of
memory on the one panel (see
TABLE 5-3:
DS70102K-page 8
dsPIC30F2010
dsPIC30F2011
dsPIC30F2012
dsPIC30F3010
dsPIC30F3011
dsPIC30F3012
dsPIC30F3013
dsPIC30F3014
dsPIC30F4011
dsPIC30F4012
dsPIC30F4013
dsPIC30F5011
dsPIC30F5013
dsPIC30F5015
dsPIC30F5016
dsPIC30F6010
dsPIC30F6010A
dsPIC30F6011
dsPIC30F6011A
dsPIC30F6012
dsPIC30F6012A
dsPIC30F6013
dsPIC30F6013A
dsPIC30F6014
dsPIC30F6014A
dsPIC30F6015
Device
Data EEPROM Programming
PROGRAMMING VERIFICATION
OVERVIEW
DATA EEPROM SIZE
Data EEPROM
Size (Words)
Computation”.
2048
2048
1024
1024
2048
2048
1024
1024
2048
2048
2048
512
512
512
512
512
512
512
512
512
512
512
512
512
0
0
Table
5-3).
Number of
Rows
128
128
128
128
128
128
128
32
32
32
32
32
32
32
32
32
32
32
32
32
64
64
64
64
0
0
5.6.2
The programming executive uses the PROGD command
to program the data EEPROM.
the flowchart of the process. Firstly, the number of rows
to program (RemainingRows) is based on the device
size, and the destination address (DestAddress) is set
to ‘0’. In this example, 128 rows (2048 words) of data
EEPROM will be programmed.
The first PROGD command programs the first row of
data EEPROM. Once the command completes
successfully, ‘RemainingRows’ is decremented by 1
and compared with 0. Since there are 127 more rows
to program, ‘BaseAddress’ is incremented by 0x20 to
point to the next row of data EEPROM. This process is
then repeated until all 128 rows of data EEPROM are
programmed.
FIGURE 5-4:
BaseAddress =
BaseAddress
+ 0x20
PROGRAMMING METHODOLOGY
No
Remaining Rows = 128
RemainingRows – 1
RemainingRows =
BaseAddress = 0
PROGD
Command with
RemainingRows
FLOWCHART FOR
PROGRAMMING
dsPIC30F6014A DATA
EEPROM
Send
BaseAddress
© 2010 Microchip Technology Inc.
PASS?
Finish
Start
0?
PROGD
Is
Is
response
Yes
Yes
Figure 5-4
Report Error
No
Failure
illustrates