AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 115
Manufacturer Part Number
IC MCU AVR32 128KB FLASH 144LQFP
Specifications of AT32UC3A0128-ALUT
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
128KB (128K x 8)
Program Memory Type
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
-40°C ~ 85°C
Package / Case
Data Bus Width
Data Ram Size
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
No. Of I/o's
Ram Memory Size
No. Of Timers
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Bonase Electronics (HK) Co., Limited
18. Flash Controller (FLASHC)
The flash controller (FLASHC) interfaces a flash block with the 32-bit internal HSB bus. Perfor-
mance for uncached systems with high clock-frequency and one wait state is increased by
placing words with sequential addresses in alternating flash subblocks. Having one read inter-
face per subblock allows them to be read in parallel. While data from one flash subblock is
being output on the bus, the sequential address is being read from the other flash subblock
and will be ready in the next clock cycle.
The controller also manages the programming, erasing, locking and unlocking sequences with
T h e H F L A S H C h a s t w o b u s c l o c k s c o n n e c t e d : O n e H i g h s p e e d b u s c l o c k
(CLK_FLASHC_HSB) and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are
generated by the Power manager. Both clocks are turned on by default, but the user has to
ensure that CLK_FLASHC_HSB is not turned off before reading the flash or writing the page-
buffer and that CLK_FLASHC_PB is not turned of before accessing the FLASHC configuration
and control registers.
The FLASHC interrupt lines are connected to internal sources of the interrupt controller. Using
FLASHC interrutps requires the interrupt controller to be programmed first.
Controls flash block with dual read ports allowing staggered reads.
Supports 0 and 1 wait state bus access.
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
32-bit HSB interface for reads from flash array and writes to page buffer.
32-bit PB interface for issuing commands to and configuration of the controller.
16 lock bits, each protecting a region consisting of (total number of pages in the flash block /
Regions can be individually protected or unprotected.
Additional protection of the Boot Loader pages.
Supports reads and writes of general-purpose NVM bits.
Supports reads and writes of additional NVM pages.
Supports device protection through a security bit.
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
Interface to Power Manager for power-down of flash-blocks in sleep mode.