AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 155

IC MCU AVR32 128KB FLASH 144LQFP

AT32UC3A0128-ALUT

Manufacturer Part Number
AT32UC3A0128-ALUT
Description
IC MCU AVR32 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets

Specifications of AT32UC3A0128-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
66 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
Controller Family/series
AT32UC3A
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
66MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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21.4.3
21.4.4
21.4.5
21.4.6
21.4.7
21.4.8
32058J–AVR32–04/11
Transfer Counter
Reload Registers
Peripheral Selection
Transfer Size
Enabling and Disabling
Interrupts
transfer. The address will be increased by either 1, 2 or 4 depending on the size of the DMA
transfer (Byte, Half-Word or Word). The Memory Address Register can be read at any time dur-
ing transfer.
Each channel has a 16-bit Transfer Counter Register (TCR). This register must be programmed
with the number of transferred to be performed. TCR should contain the number of data items to
be transferred independently of the transfer size. The Transfer Counter Register can be read at
any time during transfer to see the number of remaining transfers.
Both the Memory Address Register and the Transfer Counter Register have a reload register,
respectively Memory Address Reload Register (MARR) and Transfer Counter Reload Register
(TCRR). These registers provide the possibility for the PDCA to work on two memory buffers for
each channel. When one buffer has completed, MAR and TCR will be reloaded with the values
in MARR and TCRR. The reload logic is always enabled and will trigger if the TCR reaches zero
while TCRR holds a non-zero value.
The Peripheral Select Register decides which peripheral should be connected to the PDCA
channel. Configuring PSR will both select the direction of the transfer (memory to peripheral or
peripheral to memory), which handshake interface to use, and the address of the peripheral
holding register.
The transfer size can be set individually for each channel to be either Byte, Half-Word or Word
(8-bit, 16-bit or 32-bit respectively). Transfer size is set by programming the SIZE bit-field in the
Mode Register (MR).
Each DMA channel is enabled by writing ‘1’ to the Transfer Enable bit (TEN) in the Control Reg-
ister (CR) and disabled by writing ‘1’ to the Transfer Disable bit (TDIS). The current status can
be read from the Status Register (SR).
Interrupts can be enabled by writing to the Interrupt Enable Register (IER) and disabled by writ-
ing to Interrupt Disable Register (IDR). The Interrupt Mask Register (IMR) can be read to see
whether an interrupt is enabled or not. The current status of an interrupt source can be read
through the Interrupt Status Register (ISR).
The PDCA has three interrupt sources:
• Reload Counter Zero - The Transfer Counter Reload Register is zero.
• Transfer Finished - Both the Transfer Counter Register and Transfer Counter Reload Register
• Transfer Error - An error has occurred in accessing memory.
are zero.
AT32UC3A
155

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