AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 328
Manufacturer Part Number
IC MCU AVR32 128KB FLASH 144LQFP
Specifications of AT32UC3A0128-ALUT
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
128KB (128K x 8)
Program Memory Type
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
-40°C ~ 85°C
Package / Case
Data Bus Width
Data Ram Size
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
No. Of I/o's
Ram Memory Size
No. Of Timers
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Figure 26-31. T = 0 Protocol without Parity Error
Figure 26-32. T = 0 Protocol with Parity Error
Receive Error Counter
Receive NACK Inhibit
Transmit Character Repetition
Disable Successive Receive NACK
The USART receiver also records the total number of errors. This can be read in the Number of
Error (NER) register. The NB_ERRORS field can record up to 255 errors. Reading NER auto-
matically clears the NB_ERRORS field.
The USART can also be configured to inhibit an error. This can be achieved by setting the
INACK bit in the Mode Register (MR). If INACK is at 1, no error signal is driven on the I/O line
even if a parity bit is detected, but the INACK bit is set in the Status Register (SR). The INACK
bit can be cleared by writing the Control Register (CR) with the RSTNACK bit at 1.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding
Register, as if no error occurred. However, the RXRDY bit does not raise.
When the USART is transmitting a character and gets a NACK, it can automatically repeat the
character before moving on to the next one. Repetition is enabled by writing the
MAX_ITERATION field in the Mode Register (MR) at a value higher than 0. Each character can
be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as
the value loaded in MAX_ITERATION.
When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the
Channel Status Register (CSR). If the repetition of the character is acknowledged by the
receiver, the repetitions are stopped and the iteration counter is cleared.
The ITERATION bit in CSR can be cleared by writing the Control Register with the RSIT bit at 1.
The receiver can limit the number of successive NACKs sent back to the remote transmitter.
This is programmed by setting the bit DSNACK in the Mode Register (MR). The maximum num-
ber of NACK transmitted is programmed in the MAX_ITERATION field. As soon as