AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 413

• Manufacturer Part Number: AT32UC3A0128-ALUT
• Description: IC MCU AVR32 128KB FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, RS-485, SPI, USART
• Maximum Clock Frequency: 66 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
• Minimum Operating Temperature: - 40 C
• Controller Family/series: AT32UC3A
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 66MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.5.2
28.5.2.1
Table 28-2.
Table 28-3.
Table 28-4.
Notes:
32058J–AVR32–04/11
2
7
2
7
2
7
Bk[1:0]
2
6
2
6
2
6
Bk[1:0]
Bk[1:0]
1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0.
2
5
2
5
2
5
Software Interface
Bk[1:0]
Bk[1:0]
Bk[1:0]
32-bit Memory Data Bus Width
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
2
4
2
4
2
4
Bk[1:0]
Bk[1:0]
Bk[1:0]
2
3
2
3
2
3
Bk[1:0]
Bk[1:0]
2
2
2
2
2
2
Bk[1:0]
The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller
allows mapping different memory types according to the values set in the SDRAMC configura-
tion register.
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
user in correlation with the device structure. Various configurations are illustrated.
2
1
2
1
2
1
2
0
2
0
2
0
Row[12:0]
Row[11:0]
Table 28-2
1
9
1
9
1
9
Row[10:0]
Row[12:0]
Row[11:0]
1
8
1
8
1
8
Row[10:0]
Row[12:0]
Row[11:0]
1
7
1
7
1
7
Row[10:0]
Row[12:0]
to
Row[11:0]
1
6
1
6
1
6
Table 28-7
Row[10:0]
CPU Address Line
1
5
CPU Address Line
1
5
CPU Address Line
1
5
1
4
1
4
1
4
illustrate the SDRAM device memory mapping seen by the
1
3
1
3
1
3
1
2
1
2
1
2
1
1
1
1
1
1
1
0
1
0
1
0
9
9
9
8
Column[10:0]
8
Column[10:0]
8
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
7
7
7
Column[8:0]
Column[8:0]
Column[8:0]
Column[7:0]
Column[7:0]
Column[7:0]
6
6
6
5
5
5
AT32UC3A
4
4
4
3
3
3
2
2
2
1
1
1
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
413
0
0
0