AT32UC3A0128-ALUT Atmel, AT32UC3A0128-ALUT Datasheet - Page 443
Manufacturer Part Number
IC MCU AVR32 128KB FLASH 144LQFP
Specifications of AT32UC3A0128-ALUT
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
Program Memory Size
128KB (128K x 8)
Program Memory Type
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
-40°C ~ 85°C
Package / Case
Data Bus Width
Data Ram Size
2-Wire, RS-485, SPI, USART
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105
Minimum Operating Temperature
- 40 C
No. Of I/o's
Ram Memory Size
No. Of Timers
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Byte Address of buffer
Used. Needs to be zero for the MACB to read data from the transmit buffer. The MACB sets this to one for the first buffer
of a frame once it has been successfully transmitted.
Software has to clear this bit before the buffer can be used again.
Wrap. Marks last descriptor in transmit buffer descriptor list.
Retry limit exceeded, transmit error detected
Transmit underrun, occurs either when hresp is not OK (bus error) or the transmit data could not be fetched in time or
when buffers are exhausted in mid frame.
Buffers exhausted in mid frame
Transmit Buffer Descriptor Entry
This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used.
point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network
control, the transmit buffer queue pointer register resets to point to the beginning of the transmit
queue. Note that disabling receive does not have the same effect on the receive queue pointer.
Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start
bit of the network control register. Transmit is halted when a buffer descriptor with its used bit set
is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control
register. (Transmission is suspended if a pause frame is received while the pause enable bit is
set in the network configuration register.) Rewriting the start bit while transmission is active is
Transmission control is implemented with a Tx_go variable which is readable in the transmit sta-
tus register at bit location 3. The Tx_go variable is reset when:
To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take
effect until any ongoing transmit finishes. If a collision occurs during transmission of a multi-buf-
fer frame, transmission automatically restarts from the first buffer of the frame. If a “used” bit is
read midway through transmission of a multi-buffer frame, this is treated as a transmit error.
Transmission stops, tx_er is asserted and the FCS is bad.
If transmission stops due to a transmit error, the transmit queue pointer resets to point to the
beginning of the transmit queue. Software needs to re-initialize the transmit queue after a trans-
If transmission stops due to a “used” bit being read at the start of the frame, the transmission
queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the
transmit start bit is written
– transmit is disabled
– a buffer descriptor with its ownership bit set is read
– a new value is written to the transmit buffer queue pointer register
– bit 10, tx_halt, of the network control register is written
– there is a transmit error such as too many retries or a transmit underrun.